AHCI driver: miscellaneous changes
- check the DF status flag after each command - increase I/O timeout from 15 to 30 seconds - share some code between ATA and ATAPI after all - produce more accurate errors on DIOCEJECT - rename AHCI_ID_SIZE to the more appropriate ATA_ID_SIZE - rearrange ahci.h in a now more sensible way
This commit is contained in:
David van Moolenbroek
parent
f8c56494c9
commit
5998a4b2af
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@ -398,29 +398,6 @@ PRIVATE int atapi_check_medium(struct port_state *ps, int cmd)
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return OK;
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}
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/*===========================================================================*
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* atapi_identify *
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*===========================================================================*/
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PRIVATE void atapi_identify(struct port_state *ps)
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{
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/* Identify an ATAPI device.
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*/
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cmd_fis_t fis;
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prd_t prd;
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/* Set up a command, and a single PRD for the result. */
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memset(&fis, 0, sizeof(fis));
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fis.cf_cmd = ATA_CMD_IDENTIFY_PACKET;
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prd.prd_phys = ps->tmp_phys;
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prd.prd_size = AHCI_ID_SIZE;
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/* Start the command, but do not wait for the result. */
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port_set_cmd(ps, 0, &fis, NULL /*packet*/, &prd, 1, FALSE /*write*/);
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port_issue(ps, 0, ahci_command_timeout);
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}
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/*===========================================================================*
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* atapi_id_check *
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*===========================================================================*/
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@ -499,29 +476,6 @@ PRIVATE int atapi_transfer(struct port_state *ps, int cmd, u64_t start_lba,
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return port_exec(ps, cmd, ahci_transfer_timeout);
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}
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/*===========================================================================*
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* ata_identify *
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*===========================================================================*/
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PRIVATE void ata_identify(struct port_state *ps)
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{
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/* Identify an ATA device.
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*/
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cmd_fis_t fis;
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prd_t prd;
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/* Set up a command, and a single PRD for the result. */
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memset(&fis, 0, sizeof(fis));
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fis.cf_cmd = ATA_CMD_IDENTIFY;
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prd.prd_phys = ps->tmp_phys;
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prd.prd_size = AHCI_ID_SIZE;
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/* Start the command, but do not wait for the result. */
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port_set_cmd(ps, 0, &fis, NULL /*packet*/, &prd, 1, FALSE /*write*/);
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port_issue(ps, 0, ahci_command_timeout);
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}
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/*===========================================================================*
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* ata_id_check *
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*===========================================================================*/
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@ -609,6 +563,33 @@ PRIVATE int ata_transfer(struct port_state *ps, int cmd, u64_t start_lba,
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return port_exec(ps, cmd, ahci_transfer_timeout);
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}
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/*===========================================================================*
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* gen_identify *
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*===========================================================================*/
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PRIVATE void gen_identify(struct port_state *ps, int cmd)
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{
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/* Identify an ATA or ATAPI device.
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*/
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cmd_fis_t fis;
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prd_t prd;
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/* Set up a command, and a single PRD for the result. */
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memset(&fis, 0, sizeof(fis));
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if (ps->flags & FLAG_ATAPI)
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fis.cf_cmd = ATA_CMD_IDENTIFY_PACKET;
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else
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fis.cf_cmd = ATA_CMD_IDENTIFY;
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prd.prd_phys = ps->tmp_phys;
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prd.prd_size = ATA_ID_SIZE;
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/* Start the command, but do not wait for the result. */
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port_set_cmd(ps, cmd, &fis, NULL /*packet*/, &prd, 1, FALSE /*write*/);
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port_issue(ps, cmd, ahci_command_timeout);
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}
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/*===========================================================================*
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* ct_set_fis *
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*===========================================================================*/
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@ -1140,10 +1121,7 @@ PRIVATE void port_sig_check(struct port_state *ps)
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ps->state = STATE_WAIT_ID;
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ps->reg[AHCI_PORT_IE] = AHCI_PORT_IE_MASK;
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if (ps->flags & FLAG_ATAPI)
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atapi_identify(ps);
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else
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ata_identify(ps);
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gen_identify(ps, 0);
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}
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/*===========================================================================*
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@ -1348,13 +1326,15 @@ PRIVATE void port_intr(struct port_state *ps)
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}
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else if ((ps->flags & FLAG_BUSY) && (smask & AHCI_PORT_IS_MASK) &&
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(!(ps->reg[AHCI_PORT_TFD] & AHCI_PORT_TFD_STS_BSY) ||
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(ps->reg[AHCI_PORT_TFD] & AHCI_PORT_TFD_STS_ERR))) {
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(ps->reg[AHCI_PORT_TFD] & (AHCI_PORT_TFD_STS_ERR |
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AHCI_PORT_TFD_STS_DF)))) {
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assert(!(ps->flags & FLAG_FAILURE));
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/* Command completed or failed. */
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ps->flags &= ~FLAG_BUSY;
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if (ps->reg[AHCI_PORT_TFD] & AHCI_PORT_TFD_STS_ERR)
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if (ps->reg[AHCI_PORT_TFD] & (AHCI_PORT_TFD_STS_ERR |
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AHCI_PORT_TFD_STS_DF))
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ps->flags |= FLAG_FAILURE;
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/* Some error cases require a port restart. */
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@ -2293,21 +2273,20 @@ PRIVATE int ahci_other(struct driver *UNUSED(dp), message *m)
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if (m->m_type != DEV_IOCTL_S)
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return EINVAL;
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if (ahci_prepare(m->DEVICE) == NULL)
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return ENXIO;
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switch (m->REQUEST) {
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case DIOCEJECT:
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if (ahci_prepare(m->DEVICE) == NULL)
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return ENXIO;
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if (current_port->state != STATE_GOOD_DEV)
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return EIO;
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if (current_port->state != STATE_GOOD_DEV ||
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!(current_port->flags & FLAG_ATAPI))
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if (!(current_port->flags & FLAG_ATAPI))
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return EINVAL;
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return atapi_load_eject(current_port, 0, FALSE /*load*/);
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case DIOCOPENCT:
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if (ahci_prepare(m->DEVICE) == NULL)
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return ENXIO;
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return sys_safecopyto(m->IO_ENDPT, (cp_grant_id_t) m->IO_GRANT,
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0, (vir_bytes) ¤t_port->open_count,
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sizeof(current_port->open_count), D);
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@ -11,105 +11,13 @@
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#define SIG_TIMEOUT 250 /* time between signature checks (ms) */
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#define NR_SIG_CHECKS 60 /* maximum number of times to check */
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#define COMMAND_TIMEOUT 5000 /* time to wait for non-I/O cmd (ms) */
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#define TRANSFER_TIMEOUT 15000 /* time to wait for I/O cmd (ms) */
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#define TRANSFER_TIMEOUT 30000 /* time to wait for I/O cmd (ms) */
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/* Time values that are defined by the standards. */
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#define SPINUP_DELAY 1 /* time to assert spin-up flag (ms) */
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#define RESET_DELAY 1000 /* maximum HBA reset time (ms) */
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#define PORTREG_DELAY 500 /* maximum port register update (ms) */
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/* Host Bus Adapter (HBA) constants. */
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#define AHCI_HBA_CAP 0 /* Host Capabilities */
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#define AHCI_HBA_CAP_SNCQ (1L << 30) /* Native Cmd Queuing */
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#define AHCI_HBA_CAP_SCLO (1L << 24) /* Cmd List Override */
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#define AHCI_HBA_CAP_NCS_SHIFT 8 /* Nr of Cmd Slots */
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#define AHCI_HBA_CAP_NCS_MASK 0x1FL
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#define AHCI_HBA_CAP_NP_SHIFT 0 /* Nr of Ports */
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#define AHCI_HBA_CAP_NP_MASK 0x1FL
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#define AHCI_HBA_GHC 1 /* Global Host Control */
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#define AHCI_HBA_GHC_AE (1L << 31) /* AHCI Enable */
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#define AHCI_HBA_GHC_IE (1L << 1) /* Interrupt Enable */
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#define AHCI_HBA_GHC_HR (1L << 0) /* HBA Reset */
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#define AHCI_HBA_IS 2 /* Interrupt Status */
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#define AHCI_HBA_PI 3 /* Ports Implemented */
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#define AHCI_HBA_VS 4 /* Version */
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#define AHCI_HBA_CAP2 9 /* Host Capabilities Extended */
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/* Port constants. */
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#define AHCI_PORT_CLB 0 /* Command List Base */
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#define AHCI_PORT_CLBU 1 /* Command List Base, Upper 32 bits */
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#define AHCI_PORT_FB 2 /* FIS Base */
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#define AHCI_PORT_FBU 3 /* FIS Base, Upper 32 bits */
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#define AHCI_PORT_IS 4 /* Interrupt Status */
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#define AHCI_PORT_IS_TFES (1L << 30) /* Task File Error */
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#define AHCI_PORT_IS_HBFS (1L << 29) /* Host Bus Fatal */
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#define AHCI_PORT_IS_HBDS (1L << 28) /* Host Bus Data */
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#define AHCI_PORT_IS_IFS (1L << 27) /* Interface Fatal */
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#define AHCI_PORT_IS_PRCS (1L << 22) /* PhyRdy Change */
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#define AHCI_PORT_IS_PCS (1L << 6) /* Port Conn Change */
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#define AHCI_PORT_IS_PSS (1L << 1) /* PIO Setup FIS */
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#define AHCI_PORT_IS_DHRS (1L << 0) /* D2H Register FIS */
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#define AHCI_PORT_IS_RESTART \
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(AHCI_PORT_IS_TFES | AHCI_PORT_IS_HBFS | AHCI_PORT_IS_HBDS | \
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AHCI_PORT_IS_IFS)
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#define AHCI_PORT_IS_MASK \
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(AHCI_PORT_IS_RESTART | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS | \
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AHCI_PORT_IS_DHRS | AHCI_PORT_IS_PSS)
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#define AHCI_PORT_IE 5 /* Interrupt Enable */
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#define AHCI_PORT_IE_MASK AHCI_PORT_IS_MASK
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#define AHCI_PORT_IE_PRCE AHCI_PORT_IS_PRCS
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#define AHCI_PORT_IE_PCE AHCI_PORT_IS_PCS
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#define AHCI_PORT_IE_NONE 0L
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#define AHCI_PORT_CMD 6 /* Command and Status */
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#define AHCI_PORT_CMD_CR (1L << 15) /* Cmd List Running */
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#define AHCI_PORT_CMD_FR (1L << 14) /* FIS Recv Running */
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#define AHCI_PORT_CMD_FRE (1L << 4) /* FIS Recv Enabled */
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#define AHCI_PORT_CMD_SUD (1L << 1) /* Spin-Up Device */
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#define AHCI_PORT_CMD_ST (1L << 0) /* Start */
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#define AHCI_PORT_TFD 8 /* Task File Data */
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#define AHCI_PORT_TFD_STS_BSY (1L << 7) /* Busy */
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#define AHCI_PORT_TFD_STS_DRQ (1L << 3) /* Data Xfer Req'd */
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#define AHCI_PORT_TFD_STS_ERR (1L << 0) /* Error */
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#define AHCI_PORT_TFD_STS_INIT 0x7F /* Initial state */
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#define AHCI_PORT_SIG 9 /* Signature */
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#define ATA_SIG_ATA 0x00000101L /* ATA interface */
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#define ATA_SIG_ATAPI 0xEB140101L /* ATAPI interface */
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#define AHCI_PORT_SSTS 10 /* Serial ATA Status */
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#define AHCI_PORT_SSTS_DET_MASK 0x00000007L /* Detection Mask */
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#define AHCI_PORT_SSTS_DET_PHY 0x00000003L /* PHY Comm Establ */
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#define AHCI_PORT_SCTL 11 /* Serial ATA Control */
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#define AHCI_PORT_SCTL_DET_INIT 0x00000001L /* Perform Init Seq */
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#define AHCI_PORT_SCTL_DET_NONE 0x00000000L /* No Action Req'd */
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#define AHCI_PORT_SERR 12 /* Serial ATA Error */
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#define AHCI_PORT_SERR_DIAG_N (1L << 16) /* PhyRdy Change */
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#define AHCI_PORT_CI 14 /* Command Issue */
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/* Number of Physical Region Descriptors (PRDs). Must be at least NR_IOREQS+2,
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* and at most 1024. There is currently no reason to use more than the minimum.
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*/
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#define NR_PRDS (NR_IOREQS + 2)
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/* Various size constants. */
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#define AHCI_MEM_BASE_SIZE 0x100 /* memory-mapped base region size */
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#define AHCI_MEM_PORT_SIZE 0x80 /* memory-mapped port region size */
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#define AHCI_ID_SIZE (256 * sizeof(u16_t)) /* IDENTIFY result size */
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#define AHCI_FIS_SIZE 256 /* size of FIS receive buffer */
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#define AHCI_CL_SIZE 1024 /* size of command list buffer */
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#define AHCI_TMP_SIZE AHCI_ID_SIZE /* size of temporary storage buffer */
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#define AHCI_TMP_ALIGN 2 /* required alignment for temp buf */
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#define AHCI_CT_SIZE (128 + NR_PRDS * sizeof(u32_t) * 4)
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/* size of command table buffer */
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#define AHCI_CT_ALIGN 128 /* required alignment for CT buffer */
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#define MAX_PRD_BYTES (1L << 22) /* maximum number of bytes per PRD */
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#define MAX_TRANSFER MAX_PRD_BYTES /* maximum size of a single transfer */
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/* Command Table offsets. */
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#define AHCI_CT_PACKET_OFF 0x40 /* CT offset to ATAPI packet */
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#define AHCI_CT_PRDT_OFF 0x80 /* CT offset to PRD table */
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/* Generic FIS layout. */
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#define ATA_FIS_TYPE 0 /* FIS Type */
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#define ATA_FIS_TYPE_H2D 0x27 /* Register - Host to Device */
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@ -123,7 +31,7 @@
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#define ATA_CMD_WRITE_DMA_EXT 0x35 /* WRITE DMA EXT */
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#define ATA_CMD_PACKET 0xA0 /* PACKET */
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#define ATA_CMD_IDENTIFY_PACKET 0xA1 /* IDENTIFY PACKET DEVICE */
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#define ATA_CMD_IDENTIFY 0xEC /* IDENTIFY DEVICE */
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#define ATA_CMD_IDENTIFY 0xEC /* IDENTIFY DEVICE */
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#define ATA_H2D_FEAT 3 /* Features */
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#define ATA_FEAT_PACKET_DMA 0x01 /* use DMA */
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#define ATA_FEAT_PACKET_DMADIR 0x03 /* DMA is inbound */
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@ -144,6 +52,8 @@
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#define ATA_SECTOR_SIZE 512 /* default sector size */
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#define ATA_MAX_SECTORS 0x10000 /* max sectors per transfer */
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#define ATA_ID_SIZE (256 * sizeof(u16_t)) /* IDENTIFY result size */
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#define ATA_ID_GCAP 0 /* General capabililties */
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#define ATA_ID_GCAP_ATAPI_MASK 0xC000 /* ATAPI device mask */
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#define ATA_ID_GCAP_ATAPI 0x8000 /* ATAPI device */
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@ -201,6 +111,97 @@
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#define AHCI_CL_ATAPI (1L << 5) /* ATAPI */
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#define AHCI_CL_CFL_SHIFT 0 /* Command FIS Length */
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/* Command Table offsets. */
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#define AHCI_CT_PACKET_OFF 0x40 /* CT offset to ATAPI packet */
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#define AHCI_CT_PRDT_OFF 0x80 /* CT offset to PRD table */
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/* Host Bus Adapter (HBA) constants. */
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#define AHCI_HBA_CAP 0 /* Host Capabilities */
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#define AHCI_HBA_CAP_SNCQ (1L << 30) /* Native Cmd Queuing */
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#define AHCI_HBA_CAP_SCLO (1L << 24) /* Cmd List Override */
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#define AHCI_HBA_CAP_NCS_SHIFT 8 /* Nr of Cmd Slots */
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#define AHCI_HBA_CAP_NCS_MASK 0x1FL
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#define AHCI_HBA_CAP_NP_SHIFT 0 /* Nr of Ports */
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#define AHCI_HBA_CAP_NP_MASK 0x1FL
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#define AHCI_HBA_GHC 1 /* Global Host Control */
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#define AHCI_HBA_GHC_AE (1L << 31) /* AHCI Enable */
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#define AHCI_HBA_GHC_IE (1L << 1) /* Interrupt Enable */
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#define AHCI_HBA_GHC_HR (1L << 0) /* HBA Reset */
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#define AHCI_HBA_IS 2 /* Interrupt Status */
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#define AHCI_HBA_PI 3 /* Ports Implemented */
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#define AHCI_HBA_VS 4 /* Version */
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#define AHCI_HBA_CAP2 9 /* Host Capabilities Extended */
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/* Port constants. */
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#define AHCI_PORT_CLB 0 /* Command List Base */
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#define AHCI_PORT_CLBU 1 /* Command List Base, Upper 32 bits */
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#define AHCI_PORT_FB 2 /* FIS Base */
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#define AHCI_PORT_FBU 3 /* FIS Base, Upper 32 bits */
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#define AHCI_PORT_IS 4 /* Interrupt Status */
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#define AHCI_PORT_IS_TFES (1L << 30) /* Task File Error */
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#define AHCI_PORT_IS_HBFS (1L << 29) /* Host Bus Fatal */
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#define AHCI_PORT_IS_HBDS (1L << 28) /* Host Bus Data */
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#define AHCI_PORT_IS_IFS (1L << 27) /* Interface Fatal */
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#define AHCI_PORT_IS_PRCS (1L << 22) /* PhyRdy Change */
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#define AHCI_PORT_IS_PCS (1L << 6) /* Port Conn Change */
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#define AHCI_PORT_IS_PSS (1L << 1) /* PIO Setup FIS */
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#define AHCI_PORT_IS_DHRS (1L << 0) /* D2H Register FIS */
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#define AHCI_PORT_IS_RESTART \
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(AHCI_PORT_IS_TFES | AHCI_PORT_IS_HBFS | AHCI_PORT_IS_HBDS | \
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AHCI_PORT_IS_IFS)
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#define AHCI_PORT_IS_MASK \
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(AHCI_PORT_IS_RESTART | AHCI_PORT_IS_PRCS | AHCI_PORT_IS_PCS | \
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AHCI_PORT_IS_DHRS | AHCI_PORT_IS_PSS)
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#define AHCI_PORT_IE 5 /* Interrupt Enable */
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#define AHCI_PORT_IE_MASK AHCI_PORT_IS_MASK
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#define AHCI_PORT_IE_PRCE AHCI_PORT_IS_PRCS
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#define AHCI_PORT_IE_PCE AHCI_PORT_IS_PCS
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#define AHCI_PORT_IE_NONE 0L
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#define AHCI_PORT_CMD 6 /* Command and Status */
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#define AHCI_PORT_CMD_CR (1L << 15) /* Cmd List Running */
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#define AHCI_PORT_CMD_FR (1L << 14) /* FIS Recv Running */
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#define AHCI_PORT_CMD_FRE (1L << 4) /* FIS Recv Enabled */
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#define AHCI_PORT_CMD_SUD (1L << 1) /* Spin-Up Device */
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#define AHCI_PORT_CMD_ST (1L << 0) /* Start */
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#define AHCI_PORT_TFD 8 /* Task File Data */
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#define AHCI_PORT_TFD_STS_BSY (1L << 7) /* Busy */
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#define AHCI_PORT_TFD_STS_DF (1L << 5) /* Device Fault */
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#define AHCI_PORT_TFD_STS_DRQ (1L << 3) /* Data Xfer Req'd */
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#define AHCI_PORT_TFD_STS_ERR (1L << 0) /* Error */
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#define AHCI_PORT_TFD_STS_INIT 0x7F /* Initial state */
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#define AHCI_PORT_SIG 9 /* Signature */
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#define ATA_SIG_ATA 0x00000101L /* ATA interface */
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#define ATA_SIG_ATAPI 0xEB140101L /* ATAPI interface */
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#define AHCI_PORT_SSTS 10 /* Serial ATA Status */
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#define AHCI_PORT_SSTS_DET_MASK 0x00000007L /* Detection Mask */
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#define AHCI_PORT_SSTS_DET_PHY 0x00000003L /* PHY Comm Establ */
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#define AHCI_PORT_SCTL 11 /* Serial ATA Control */
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#define AHCI_PORT_SCTL_DET_INIT 0x00000001L /* Perform Init Seq */
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#define AHCI_PORT_SCTL_DET_NONE 0x00000000L /* No Action Req'd */
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#define AHCI_PORT_SERR 12 /* Serial ATA Error */
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#define AHCI_PORT_SERR_DIAG_N (1L << 16) /* PhyRdy Change */
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#define AHCI_PORT_CI 14 /* Command Issue */
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/* Number of Physical Region Descriptors (PRDs). Must be at least NR_IOREQS+2,
|
||||
* and at most 1024. There is currently no reason to use more than the minimum.
|
||||
*/
|
||||
#define NR_PRDS (NR_IOREQS + 2)
|
||||
|
||||
/* Various size constants. */
|
||||
#define AHCI_MEM_BASE_SIZE 0x100 /* memory-mapped base region size */
|
||||
#define AHCI_MEM_PORT_SIZE 0x80 /* memory-mapped port region size */
|
||||
|
||||
#define AHCI_FIS_SIZE 256 /* size of FIS receive buffer */
|
||||
#define AHCI_CL_SIZE 1024 /* size of command list buffer */
|
||||
#define AHCI_TMP_SIZE ATA_ID_SIZE /* size of temporary storage buffer */
|
||||
#define AHCI_TMP_ALIGN 2 /* required alignment for temp buf */
|
||||
#define AHCI_CT_SIZE (128 + NR_PRDS * sizeof(u32_t) * 4)
|
||||
/* size of command table buffer */
|
||||
#define AHCI_CT_ALIGN 128 /* required alignment for CT buffer */
|
||||
|
||||
#define MAX_PRD_BYTES (1L << 22) /* maximum number of bytes per PRD */
|
||||
#define MAX_TRANSFER MAX_PRD_BYTES /* maximum size of a single transfer */
|
||||
|
||||
/* Command Frame Information Structure (FIS). For internal use only;
|
||||
* the contents of this structure are later converted to an actual FIS.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue