at_wini/ahci: write cache ioctls
This commit is contained in:
David van Moolenbroek
parent
5998a4b2af
commit
484b2f43d6
5 changed files with 188 additions and 9 deletions
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@ -178,6 +178,7 @@ PRIVATE long ahci_sig_timeout = SIG_TIMEOUT;
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PRIVATE long ahci_sig_checks = NR_SIG_CHECKS;
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PRIVATE long ahci_command_timeout = COMMAND_TIMEOUT;
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PRIVATE long ahci_transfer_timeout = TRANSFER_TIMEOUT;
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PRIVATE long ahci_flush_timeout = FLUSH_TIMEOUT;
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PRIVATE int ahci_map[MAX_DRIVES]; /* device-to-port mapping */
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@ -437,6 +438,19 @@ PRIVATE int atapi_id_check(struct port_state *ps, u16_t *buf)
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ATA_ID_GCAP_TYPE_SHIFT) == ATAPI_TYPE_CDROM)
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ps->flags |= FLAG_READONLY;
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if ((buf[ATA_ID_SUP1] & ATA_ID_SUP1_VALID_MASK) == ATA_ID_SUP1_VALID &&
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!(ps->flags & FLAG_READONLY)) {
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/* Save write cache related capabilities of the device. It is
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* possible, although unlikely, that a device has support for
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* either of these but not both.
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*/
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if (buf[ATA_ID_SUP0] & ATA_ID_SUP0_WCACHE)
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ps->flags |= FLAG_HAS_WCACHE;
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if (buf[ATA_ID_SUP1] & ATA_ID_SUP1_FLUSH)
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ps->flags |= FLAG_HAS_FLUSH;
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}
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return TRUE;
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}
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@ -486,15 +500,16 @@ PRIVATE int ata_id_check(struct port_state *ps, u16_t *buf)
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*/
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/* This must be an ATA device; it must not have removable media;
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* it must support LBA and DMA; it must support 48-bit addressing.
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* it must support LBA and DMA; it must support the FLUSH CACHE
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* command; it must support 48-bit addressing.
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*/
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if ((buf[ATA_ID_GCAP] & (ATA_ID_GCAP_ATA_MASK | ATA_ID_GCAP_REMOVABLE |
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ATA_ID_GCAP_INCOMPLETE)) != ATA_ID_GCAP_ATA ||
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(buf[ATA_ID_CAP] & (ATA_ID_CAP_LBA | ATA_ID_CAP_DMA)) !=
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(ATA_ID_CAP_LBA | ATA_ID_CAP_DMA) ||
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(buf[ATA_ID_SUP1] &
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(ATA_ID_SUP1_VALID_MASK | ATA_ID_SUP1_LBA48)) !=
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(ATA_ID_SUP1_VALID | ATA_ID_SUP1_LBA48)) {
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(buf[ATA_ID_SUP1] & (ATA_ID_SUP1_VALID_MASK |
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ATA_ID_SUP1_FLUSH | ATA_ID_SUP1_LBA48)) !=
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(ATA_ID_SUP1_VALID | ATA_ID_SUP1_FLUSH | ATA_ID_SUP1_LBA48)) {
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dprintf(V_ERR, ("%s: unsupported ATA device\n",
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ahci_portname(ps)));
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@ -527,7 +542,11 @@ PRIVATE int ata_id_check(struct port_state *ps, u16_t *buf)
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return FALSE;
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}
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ps->flags |= FLAG_HAS_MEDIUM;
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ps->flags |= FLAG_HAS_MEDIUM | FLAG_HAS_FLUSH;
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/* FLUSH CACHE is mandatory for ATA devices; write caches are not. */
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if (buf[ATA_ID_SUP0] & ATA_ID_SUP0_WCACHE)
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ps->flags |= FLAG_HAS_WCACHE;
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return TRUE;
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}
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@ -566,9 +585,10 @@ PRIVATE int ata_transfer(struct port_state *ps, int cmd, u64_t start_lba,
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/*===========================================================================*
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* gen_identify *
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*===========================================================================*/
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PRIVATE void gen_identify(struct port_state *ps, int cmd)
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PRIVATE int gen_identify(struct port_state *ps, int cmd, int blocking)
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{
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/* Identify an ATA or ATAPI device.
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/* Identify an ATA or ATAPI device. If the blocking flag is set, block
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* until the command has completed; otherwise return immediately.
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*/
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cmd_fis_t fis;
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prd_t prd;
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@ -584,10 +604,102 @@ PRIVATE void gen_identify(struct port_state *ps, int cmd)
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prd.prd_phys = ps->tmp_phys;
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prd.prd_size = ATA_ID_SIZE;
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/* Start the command, but do not wait for the result. */
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/* Start the command, and possibly wait for the result. */
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port_set_cmd(ps, cmd, &fis, NULL /*packet*/, &prd, 1, FALSE /*write*/);
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if (blocking)
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return port_exec(ps, cmd, ahci_command_timeout);
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port_issue(ps, cmd, ahci_command_timeout);
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return OK;
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}
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/*===========================================================================*
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* gen_flush_wcache *
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*===========================================================================*/
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PRIVATE int gen_flush_wcache(struct port_state *ps, int cmd)
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{
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/* Flush the device's write cache.
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*/
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cmd_fis_t fis;
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/* The FLUSH CACHE command may not be supported by all (writable ATAPI)
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* devices.
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*/
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if (!(ps->flags & FLAG_HAS_FLUSH))
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return EINVAL;
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/* Use the FLUSH CACHE command for both ATA and ATAPI. We are not
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* interested in the disk location of a failure, so there is no reason
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* to use the ATA-only FLUSH CACHE EXT command. Either way, the command
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* may indeed fail due to a disk error, in which case it should be
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* repeated. For now, we shift this responsibility onto the caller.
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*/
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memset(&fis, 0, sizeof(fis));
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fis.cf_cmd = ATA_CMD_FLUSH_CACHE;
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/* Start the command, and wait for it to complete or fail.
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* The flush command may take longer than regular I/O commands.
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*/
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port_set_cmd(ps, cmd, &fis, NULL /*packet*/, NULL /*prdt*/, 0,
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FALSE /*write*/);
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return port_exec(ps, cmd, ahci_flush_timeout);
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}
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/*===========================================================================*
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* gen_get_wcache *
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*===========================================================================*/
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PRIVATE int gen_get_wcache(struct port_state *ps, int cmd, int *val)
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{
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/* Retrieve the status of the device's write cache.
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*/
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int r;
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/* Write caches are not mandatory. */
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if (!(ps->flags & FLAG_HAS_WCACHE))
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return EINVAL;
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/* Retrieve information about the device. */
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if ((r = gen_identify(ps, cmd, TRUE /*blocking*/)) != OK)
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return r;
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/* Return the current setting. */
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*val = !!(((u16_t *) ps->tmp_base)[ATA_ID_ENA0] & ATA_ID_ENA0_WCACHE);
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return OK;
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}
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/*===========================================================================*
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* gen_set_wcache *
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*===========================================================================*/
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PRIVATE int gen_set_wcache(struct port_state *ps, int cmd, int enable)
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{
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/* Enable or disable the device's write cache.
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*/
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cmd_fis_t fis;
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clock_t timeout;
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/* Write caches are not mandatory. */
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if (!(ps->flags & FLAG_HAS_WCACHE))
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return EINVAL;
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/* Disabling the write cache causes a (blocking) cache flush. Cache
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* flushes may take much longer than regular commands.
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*/
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timeout = enable ? ahci_command_timeout : ahci_flush_timeout;
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/* Set up a command. */
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memset(&fis, 0, sizeof(fis));
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fis.cf_cmd = ATA_CMD_SET_FEATURES;
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fis.cf_feat = enable ? ATA_SF_EN_WCACHE : ATA_SF_DI_WCACHE;
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/* Start the command, and wait for it to complete or fail. */
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port_set_cmd(ps, cmd, &fis, NULL /*packet*/, NULL /*prdt*/, 0,
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FALSE /*write*/);
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return port_exec(ps, cmd, timeout);
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}
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/*===========================================================================*
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@ -1121,7 +1233,7 @@ PRIVATE void port_sig_check(struct port_state *ps)
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ps->state = STATE_WAIT_ID;
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ps->reg[AHCI_PORT_IE] = AHCI_PORT_IE_MASK;
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gen_identify(ps, 0);
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(void) gen_identify(ps, 0, FALSE /*blocking*/);
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}
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/*===========================================================================*
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@ -1799,6 +1911,9 @@ PRIVATE void ahci_stop(void)
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for (port = 0; port < hba_state.nr_ports; port++) {
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if (port_state[port].state != STATE_NO_PORT) {
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if (port_state[port].state == STATE_GOOD_DEV)
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(void) gen_flush_wcache(&port_state[port], 0);
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port_stop(&port_state[port]);
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port_free(&port_state[port]);
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@ -1896,6 +2011,7 @@ PRIVATE void ahci_get_params(void)
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ahci_get_var("ahci_sig_checks", &ahci_sig_checks, FALSE);
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ahci_get_var("ahci_cmd_timeout", &ahci_command_timeout, TRUE);
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ahci_get_var("ahci_io_timeout", &ahci_transfer_timeout, TRUE);
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ahci_get_var("ahci_flush_timeout", &ahci_flush_timeout, TRUE);
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}
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/*===========================================================================*
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@ -2269,6 +2385,7 @@ PRIVATE int ahci_other(struct driver *UNUSED(dp), message *m)
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/* Process any messages not covered by the other calls.
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* This function only implements IOCTLs.
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*/
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int r, val;
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if (m->m_type != DEV_IOCTL_S)
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return EINVAL;
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@ -2290,6 +2407,33 @@ PRIVATE int ahci_other(struct driver *UNUSED(dp), message *m)
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return sys_safecopyto(m->IO_ENDPT, (cp_grant_id_t) m->IO_GRANT,
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0, (vir_bytes) ¤t_port->open_count,
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sizeof(current_port->open_count), D);
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case DIOCFLUSH:
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if (current_port->state != STATE_GOOD_DEV)
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return EIO;
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return gen_flush_wcache(current_port, 0);
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case DIOCSETWC:
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if (current_port->state != STATE_GOOD_DEV)
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return EIO;
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if ((r = sys_safecopyfrom(m->IO_ENDPT,
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(cp_grant_id_t) m->IO_GRANT, 0, (vir_bytes) &val,
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sizeof(val), D)) != OK)
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return r;
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return gen_set_wcache(current_port, 0, val);
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case DIOCGETWC:
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if (current_port->state != STATE_GOOD_DEV)
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return EIO;
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if ((r = gen_get_wcache(current_port, 0, &val)) != OK)
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return r;
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return sys_safecopyto(m->IO_ENDPT, (cp_grant_id_t) m->IO_GRANT,
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0, (vir_bytes) &val, sizeof(val), D);
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}
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return EINVAL;
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@ -12,6 +12,7 @@
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#define NR_SIG_CHECKS 60 /* maximum number of times to check */
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#define COMMAND_TIMEOUT 5000 /* time to wait for non-I/O cmd (ms) */
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#define TRANSFER_TIMEOUT 30000 /* time to wait for I/O cmd (ms) */
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#define FLUSH_TIMEOUT 60000 /* time to wait for flush cmd (ms) */
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/* Time values that are defined by the standards. */
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#define SPINUP_DELAY 1 /* time to assert spin-up flag (ms) */
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@ -31,7 +32,9 @@
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#define ATA_CMD_WRITE_DMA_EXT 0x35 /* WRITE DMA EXT */
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#define ATA_CMD_PACKET 0xA0 /* PACKET */
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#define ATA_CMD_IDENTIFY_PACKET 0xA1 /* IDENTIFY PACKET DEVICE */
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#define ATA_CMD_FLUSH_CACHE 0xE7 /* FLUSH CACHE */
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#define ATA_CMD_IDENTIFY 0xEC /* IDENTIFY DEVICE */
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#define ATA_CMD_SET_FEATURES 0xEF /* SET FEATURES */
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#define ATA_H2D_FEAT 3 /* Features */
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#define ATA_FEAT_PACKET_DMA 0x01 /* use DMA */
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#define ATA_FEAT_PACKET_DMADIR 0x03 /* DMA is inbound */
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@ -69,10 +72,18 @@
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#define ATA_ID_DMADIR 62 /* DMADIR */
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#define ATA_ID_DMADIR_DMADIR 0x8000 /* DMADIR required */
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#define ATA_ID_DMADIR_DMA 0x0400 /* DMA supported (DMADIR) */
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#define ATA_ID_SUP0 82 /* Features supported (1/3) */
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#define ATA_ID_SUP0_WCACHE 0x0020 /* Write cache supported */
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#define ATA_ID_SUP1 83 /* Features supported (2/3) */
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#define ATA_ID_SUP1_VALID_MASK 0xC000 /* Word validity mask */
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#define ATA_ID_SUP1_VALID 0x4000 /* Word contents are valid */
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#define ATA_ID_SUP1_FLUSH 0x1000 /* FLUSH CACHE supported */
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#define ATA_ID_SUP1_LBA48 0x0400 /* 48-bit LBA supported */
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#define ATA_ID_ENA0 85 /* Features enabled (1/3) */
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#define ATA_ID_ENA0_WCACHE 0x0020 /* Write cache enabled */
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#define ATA_ID_ENA2 87 /* Features enabled (3/3) */
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#define ATA_ID_ENA2_VALID_MASK 0xC000 /* Word validity mask */
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#define ATA_ID_ENA2_VALID 0x4000 /* Word contents are valid */
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#define ATA_ID_LBA0 100 /* Max. LBA48 address (LSW) */
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#define ATA_ID_LBA1 101 /* Max. LBA48 address */
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#define ATA_ID_LBA2 102 /* Max. LBA48 address */
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@ -84,6 +95,9 @@
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#define ATA_ID_LSS0 118 /* Logical sector size (LSW) */
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#define ATA_ID_LSS1 119 /* Logical sector size (MSW) */
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#define ATA_SF_EN_WCACHE 0x02 /* Enable write cache */
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#define ATA_SF_DI_WCACHE 0x82 /* Disable write cache */
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/* ATAPI constants. */
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#define ATAPI_PACKET_SIZE 16 /* ATAPI packet size */
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@ -254,6 +268,8 @@ enum {
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#define FLAG_BUSY 0x00000010 /* is an operation ongoing? */
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#define FLAG_FAILURE 0x00000020 /* did the operation fail? */
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#define FLAG_BARRIER 0x00000040 /* no access until unset */
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#define FLAG_HAS_WCACHE 0x00000080 /* is a write cache present? */
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#define FLAG_HAS_FLUSH 0x00000100 /* is FLUSH CACHE supported? */
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/* Mapping between devices and ports. */
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#define NO_PORT -1 /* this device maps to no port */
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@ -2297,6 +2297,7 @@ struct driver *dr;
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message *m;
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{
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int r, timeout, prev;
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struct command cmd;
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if (m->m_type != DEV_IOCTL_S )
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return EINVAL;
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@ -2353,6 +2354,20 @@ message *m;
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return r;
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return OK;
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} else if (m->REQUEST == DIOCFLUSH) {
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if (w_prepare(m->DEVICE) == NULL) return ENXIO;
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if (w_wn->state & ATAPI) return EINVAL;
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if (!(w_wn->state & INITIALIZED) && w_specify() != OK)
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return EIO;
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cmd.command = CMD_FLUSH_CACHE;
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if (com_simple(&cmd) != OK || !w_waitfor(STATUS_BSY, 0))
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return EIO;
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return (w_wn->w_status & (STATUS_ERR|STATUS_WF)) ? EIO : OK;
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}
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return EINVAL;
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}
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@ -68,6 +68,7 @@
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#define CMD_SPECIFY 0x91 /* specify parameters */
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#define CMD_READ_DMA 0xC8 /* read data using DMA */
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#define CMD_WRITE_DMA 0xCA /* write data using DMA */
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#define CMD_FLUSH_CACHE 0xE7 /* flush the write cache */
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#define ATA_IDENTIFY 0xEC /* identify drive */
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/* #define REG_CTL 0x206 */ /* control register */
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#define REG_CTL 0 /* control register */
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@ -13,5 +13,8 @@
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#define DIOCEJECT _IO ('d', 5)
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#define DIOCTIMEOUT _IORW('d', 6, int)
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#define DIOCOPENCT _IOR('d', 7, int)
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#define DIOCFLUSH _IO ('d', 8)
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#define DIOCSETWC _IOW('d', 9, int)
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#define DIOCGETWC _IOR('d', 10, int)
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#endif /* _S_I_DISK_H */
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