kernel: add padconf kernel call
On the AM335X, writes to the padconf registers must be done in privileged mode. To allow userspace drivers to dynamically change the padconf at runtime, a kernel call has been added. Change-Id: I4b25d2879399b1785a360912faa0e90b5c258533
This commit is contained in:
Thomas Cort
parent
c8f3b10909
commit
4593804bf0
24 changed files with 161 additions and 505 deletions
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@ -828,6 +828,7 @@ struct
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{ "STIME", SYS_STIME },
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{ "VMCTL", SYS_VMCTL },
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{ "MEMSET", SYS_MEMSET },
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{ "PADCONF", SYS_PADCONF },
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{ NULL, 0 }
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};
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@ -103,8 +103,6 @@
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./usr/lib/libgpio_pic.a minix-sys
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./usr/lib/libi2cdriver.a minix-sys
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./usr/lib/libi2cdriver_pic.a minix-sys
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./usr/lib/libpadconf.a minix-sys
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./usr/lib/libpadconf_pic.a minix-sys
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./usr/man/man1/eepromread.1 minix-sys
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./usr/mdec minix-sys
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./usr/sbin/bmp085 minix-sys
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@ -3,7 +3,7 @@ PROG= gpio
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SRCS= gpio.c
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DPADD+= ${LIBBLOCKDRIVER} ${LIBSYS}
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LDADD+= -lvtreefs -lsys -lgpio -lpadconf -lclkconf
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LDADD+= -lvtreefs -lsys -lgpio -lclkconf
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#
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# This is a system driver.
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@ -169,18 +169,14 @@ init_hook(void)
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add_gpio_inode("USR1", 150, GPIO_MODE_OUTPUT);
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add_gpio_inode("Button", 4, GPIO_MODE_INPUT);
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/* configure the padconf */
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padconf_init();
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/* configure GPIO_144 to be exported */
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padconf_set(CONTROL_PADCONF_UART2_CTS, 0xff,
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sys_padconf(CONTROL_PADCONF_UART2_CTS, 0xff,
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PADCONF_MUXMODE(4) | PADCONF_PULL_MODE_PD_EN |
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PADCONF_INPUT_ENABLE(1));
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padconf_set(CONTROL_PADCONF_MMC2_DAT6, 0xff00,
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sys_padconf(CONTROL_PADCONF_MMC2_DAT6, 0xff00,
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(PADCONF_MUXMODE(4) | PADCONF_PULL_MODE_PD_EN |
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PADCONF_INPUT_ENABLE(1)) << 16);
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padconf_release();
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/* Added for demo purposes */
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add_gpio_inode("BigRedButton", 144, GPIO_MODE_INPUT);
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add_gpio_inode("BigRedButtonLed", 139, GPIO_MODE_OUTPUT);
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@ -6,8 +6,8 @@ PROG= i2c
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SRCS+= i2c.c
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DPADD+= ${LIBCHARDRIVER} ${LIBSYS} ${LIBTIMERS} ${CLKCONF} ${PADCONF}
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LDADD+= -lchardriver -lsys -ltimers -lclkconf -lpadconf
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DPADD+= ${LIBCHARDRIVER} ${LIBSYS} ${LIBTIMERS} ${CLKCONF}
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LDADD+= -lchardriver -lsys -ltimers -lclkconf
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MAN=
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@ -217,9 +217,7 @@ static uint16_t omap_i2c_poll(uint16_t mask);
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static int omap_i2c_bus_is_free(void);
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static int omap_i2c_soft_reset(void);
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static void omap_i2c_bus_init(void);
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#if 0
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static void omap_i2c_padconf(int i2c_bus_id);
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#endif /* disable until libpadconf is fixed */
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static void omap_i2c_clkconf(int i2c_bus_id);
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static void omap_i2c_intr_enable(void);
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static uint16_t omap_i2c_read_status(void);
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@ -391,15 +389,12 @@ omap_i2c_clkconf(int i2c_bus_id)
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clkconf_release();
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}
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#if 0
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/* re-enable this code when libpadconf is working */
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static void
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omap_i2c_padconf(int i2c_bus_id)
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{
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int r;
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u32_t pinopts;
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padconf_init();
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if (omap_i2c_bus->bus_type == AM335X_I2C_BUS) {
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/* use the options suggested in starterware driver */
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@ -410,28 +405,55 @@ omap_i2c_padconf(int i2c_bus_id)
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switch (i2c_bus_id) {
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case 0:
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pinopts |= CONTROL_CONF_MUXMODE(0);
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padconf_set(CONTROL_CONF_I2C0_SDA, 0xffffffff,
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r = sys_padconf(CONTROL_CONF_I2C0_SDA, 0xffffffff,
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pinopts);
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padconf_set(CONTROL_CONF_I2C0_SCL, 0xffffffff,
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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r = sys_padconf(CONTROL_CONF_I2C0_SCL, 0xffffffff,
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pinopts);
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log_info(&log, "pinopts=%x\n", pinopts);
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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log_debug(&log, "pinopts=0x%x\n", pinopts);
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break;
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case 1:
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pinopts |= CONTROL_CONF_MUXMODE(2);
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padconf_set(CONTROL_CONF_SPI0_CS0, 0xffffffff,
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r = sys_padconf(CONTROL_CONF_SPI0_CS0, 0xffffffff,
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pinopts);
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padconf_set(CONTROL_CONF_SPI0_D1, 0xffffffff, pinopts);
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log_info(&log, "pinopts=%x\n", pinopts);
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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r = sys_padconf(CONTROL_CONF_SPI0_D1, 0xffffffff,
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pinopts);
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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log_debug(&log, "pinopts=0x%x\n", pinopts);
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break;
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case 2:
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pinopts |= CONTROL_CONF_MUXMODE(3);
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padconf_set(CONTROL_CONF_UART1_CTSN,
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r = sys_padconf(CONTROL_CONF_UART1_CTSN, 0xffffffff,
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pinopts);
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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r = sys_padconf(CONTROL_CONF_UART1_RTSN,
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0xffffffff, pinopts);
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padconf_set(CONTROL_CONF_UART1_RTSN,
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0xffffffff, pinopts);
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log_info(&log, "pinopts=%x\n", pinopts);
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if (r != OK) {
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log_warn(&log, "padconf failed (r=%d)\n", r);
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}
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log_debug(&log, "pinopts=0x%x\n", pinopts);
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break;
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default:
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@ -441,10 +463,7 @@ omap_i2c_padconf(int i2c_bus_id)
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}
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/* nothing to do for the DM37XX */
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padconf_release();
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}
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#endif
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static int
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omap_i2c_soft_reset(void)
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@ -787,6 +806,9 @@ omap_interface_setup(int (**process) (minix_i2c_ioctl_exec_t * ioctl_exec),
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/* select the bus to operate on */
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omap_i2c_bus = &omap_i2c_buses[i2c_bus_id];
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/* Configure Pins */
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omap_i2c_padconf(i2c_bus_id);
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/*
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* Map I2C Registers
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*/
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@ -811,12 +833,6 @@ omap_interface_setup(int (**process) (minix_i2c_ioctl_exec_t * ioctl_exec),
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/* Enable Clocks */
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omap_i2c_clkconf(i2c_bus_id);
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#if 0
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/* disable until libpadconf is fixed */
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/* Configure Pins */
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omap_i2c_padconf(i2c_bus_id);
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#endif
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/* Perform a soft reset of the I2C module to ensure a fresh start */
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r = omap_i2c_soft_reset();
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if (r != OK) {
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@ -582,6 +582,7 @@ service gpio
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system
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PRIVCTL # 4
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IRQCTL # 19
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PADCONF # 57
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;
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irq
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29 # GPIO module 1
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@ -599,6 +600,7 @@ service i2c
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system
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PRIVCTL # 4
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IRQCTL # 19
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PADCONF # 57
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;
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irq
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# DM37XX (BeagleBoard-xM)
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@ -359,8 +359,10 @@
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# define SYS_SAFEMEMSET (KERNEL_CALL + 56) /* sys_safememset() */
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# define SYS_PADCONF (KERNEL_CALL + 57) /* sys_padconf() */
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/* Total */
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#define NR_SYS_CALLS 57 /* number of kernel calls */
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#define NR_SYS_CALLS 58 /* number of kernel calls */
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#define SYS_CALL_MASK_SIZE BITMAP_CHUNKS(NR_SYS_CALLS)
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@ -684,6 +686,11 @@
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#define SCHEDCTL_PRIORITY m9_s4 /* current scheduling priority */
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#define SCHEDCTL_CPU m9_l5 /* where to place this process */
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/* Field names for SYS_PADCONF */
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#define PADCONF_PADCONF m2_i1 /* pad to configure */
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#define PADCONF_MASK m2_i2 /* mask to apply */
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#define PADCONF_VALUE m2_i3 /* value to write */
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/*===========================================================================*
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* Messages for the Reincarnation Server *
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*===========================================================================*/
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@ -1,10 +1,18 @@
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#ifndef __PADCONF_H__
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#define __PADCONF_H__
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#ifndef __MINIX_PADCONF_H
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#define __MINIX_PADCONF_H
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/* Define the start address of the padconf registers and the size of the block.
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* The base must be page aligned, so we round down and the kernel adds the
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* offset. The size must be a multiple of ARM_PAGE_SIZE, so we round up to 4KB.
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*/
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#ifdef AM335X
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#define PADCONF_REGISTERS_BASE 0x44E10000
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#define PADCONF_REGISTERS_OFFSET 0x0000
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#define PADCONF_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
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#elif DM37XX
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#define PADCONF_REGISTERS_BASE 0x48002030
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#define PADCONF_REGISTERS_BASE 0x48002000
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#define PADCONF_REGISTERS_OFFSET 0x0030
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#define PADCONF_REGISTERS_SIZE 0x1000 /* OFFSET + highest reg, rounded up */
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#endif
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#define PADCONF_MUXMODE(X) (X & 0x7) /* mode 1 til 7 [2:0] */
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@ -314,8 +322,4 @@
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#define CONTROL_CONF_PUDEN (1<<3)
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#define CONTROL_CONF_MUXMODE(X) (X&0x7)
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int padconf_init(void);
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int padconf_set(u32_t padconf, u32_t mask, u32_t value);
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int padconf_release(void);
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#endif /* __PADCONF_H__ */
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#endif /* __MINIX_PADCONF_H */
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@ -215,6 +215,9 @@ int sys_out(int port, u32_t value, int type);
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#define sys_inl(p,v) sys_in((p), (v), _DIO_LONG)
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int sys_in(int port, u32_t *value, int type);
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/* arm pinmux */
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int sys_padconf(u32_t padconf, u32_t mask, u32_t value);
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/* pci.c */
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void pci_init(void);
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int pci_first_dev(int *devindp, u16_t *vidp, u16_t *didp);
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@ -128,8 +128,8 @@ void arch_init(void)
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value = OMAP_PMUSERENR_EN;
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asm volatile ("MCR p15, 0, %0, c9, c14, 0\t\n": : "r" (value));
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/* configure i2c pinmux */
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omap3_padconf_init();
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/* map memory for padconf */
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arch_padconf_init();
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/* map memory for rtc */
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omap3_rtc_init();
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@ -1,14 +1,11 @@
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/* temporary padconf work-around
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*
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* pinmux must be configured in privileged mode on the Cortex-A8. This code
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* does a simple static configuration of a few pins. It's only here until
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* a proper padconf server that does kernel calls can be developed.
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*/
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/* Implements sys_padconf() for the AM335X and DM37XX. */
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#include "kernel/kernel.h"
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#include "arch_proto.h"
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#include <sys/types.h>
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#include <machine/cpu.h>
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#include <minix/mmio.h>
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#include <minix/padconf.h>
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#include <assert.h>
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#include <io.h>
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#include <stdlib.h>
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@ -16,47 +13,39 @@
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#include "omap_padconf.h"
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u32_t base = PADCONF_REGISTERS_BASE;
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static int kernel_padconf_set(u32_t padconf, u32_t mask, u32_t value);
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static int
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kernel_padconf_set(u32_t padconf, u32_t mask, u32_t value)
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struct omap_padconf
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{
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assert(padconf <= CONTROL_CONF_USB1_DRVVBUS);
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set32(base + padconf, mask, value);
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vir_bytes base;
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vir_bytes offset;
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vir_bytes size;
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};
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static struct omap_padconf omap_padconf = {
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.base = PADCONF_REGISTERS_BASE,
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.offset = PADCONF_REGISTERS_OFFSET,
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.size = PADCONF_REGISTERS_SIZE
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};
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static kern_phys_map padconf_phys_map;
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int
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arch_padconf_set(u32_t padconf, u32_t mask, u32_t value)
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{
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/* check that the value will be inside the padconf memory range */
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if (padconf >= (PADCONF_REGISTERS_SIZE - PADCONF_REGISTERS_OFFSET)) {
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return EINVAL; /* outside of valid range */
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}
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set32(padconf + omap_padconf.base + omap_padconf.offset, mask, value);
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return OK;
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}
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void
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omap3_padconf_init(void)
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arch_padconf_init(void)
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{
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kern_phys_map_ptr(omap_padconf.base, omap_padconf.size,
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&padconf_phys_map, &omap_padconf.base);
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#ifdef AM335X
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u32_t pinopts, value;
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/* Common options for BeagleBone I2C Pins */
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pinopts = CONTROL_CONF_SLEWCTRL | CONTROL_CONF_RXACTIVE |
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CONTROL_CONF_PUTYPESEL;
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/* I2C0 */
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value = pinopts | CONTROL_CONF_MUXMODE(0);
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kernel_padconf_set(CONTROL_CONF_I2C0_SDA, 0xffffffff, value);
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kernel_padconf_set(CONTROL_CONF_I2C0_SCL, 0xffffffff, value);
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/* I2C1 */
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value = pinopts | CONTROL_CONF_MUXMODE(2);
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kernel_padconf_set(CONTROL_CONF_SPI0_CS0, 0xffffffff, value);
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kernel_padconf_set(CONTROL_CONF_SPI0_D1, 0xffffffff, value);
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/* I2C2 */
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value = pinopts | CONTROL_CONF_MUXMODE(3);
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kernel_padconf_set(CONTROL_CONF_UART1_CTSN, 0xffffffff, value);
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kernel_padconf_set(CONTROL_CONF_UART1_RTSN, 0xffffffff, value);
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#endif
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/* nothing to do for DM37XX */
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return;
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}
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@ -1,11 +1,10 @@
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#ifndef _OMAP_PADCONF_H
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#define _OMAP_PADCONF_H
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#include "omap_padconf_registers.h"
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#ifndef __ASSEMBLY__
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void omap3_padconf_init(void);
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void arch_padconf_init(void);
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int arch_padconf_set(u32_t padconf, u32_t mask, u32_t value);
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#endif /* __ASSEMBLY__ */
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@ -1,317 +0,0 @@
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#ifndef __OMAP_PADCONF_REGISTERS_H
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#define __OMAP_PADCONF_REGISTERS_H
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#ifdef AM335X
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#define PADCONF_REGISTERS_BASE 0x44E10000
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#elif DM37XX
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#define PADCONF_REGISTERS_BASE 0x48002030
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#endif
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#define PADCONF_MUXMODE(X) (X & 0x7) /* mode 1 til 7 [2:0] */
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#define PADCONF_PULL_MODE(X) ((X & 0x3) << 3) /* 2 bits[4:3] */
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#define PADCONF_PULL_MODE_PD_DIS PADCONF_PULL_MODE(0) /* pull down disabled */
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#define PADCONF_PULL_MODE_PD_EN PADCONF_PULL_MODE(1) /* pull down enabled */
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#define PADCONF_PULL_MODE_PU_DIS PADCONF_PULL_MODE(2) /* pull up disabled */
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#define PADCONF_PULL_MODE_PU_EN PADCONF_PULL_MODE(3) /* pull up enabled */
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#define PADCONF_INPUT_ENABLE(X) ((X & 0x1) << 8) /* 1 bits[8] */
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#define PADCONF_OFF_MODE(X) ((X & 0xFE) << 9) /* 5 bits[13:9] */
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/* padconf pin definitions */
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#define CONTROL_PADCONF_SDRC_D0 (0x00000000)
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#define CONTROL_PADCONF_SDRC_D2 (0x00000004)
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#define CONTROL_PADCONF_SDRC_D4 (0x00000008)
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#define CONTROL_PADCONF_SDRC_D6 (0x0000000C)
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#define CONTROL_PADCONF_SDRC_D8 (0x00000010)
|
||||
#define CONTROL_PADCONF_SDRC_D10 (0x00000014)
|
||||
#define CONTROL_PADCONF_SDRC_D12 (0x00000018)
|
||||
#define CONTROL_PADCONF_SDRC_D14 (0x0000001C)
|
||||
#define CONTROL_PADCONF_SDRC_D16 (0x00000020)
|
||||
#define CONTROL_PADCONF_SDRC_D18 (0x00000024)
|
||||
#define CONTROL_PADCONF_SDRC_D20 (0x00000028)
|
||||
#define CONTROL_PADCONF_SDRC_D22 (0x0000002C)
|
||||
#define CONTROL_PADCONF_SDRC_D24 (0x00000030)
|
||||
#define CONTROL_PADCONF_SDRC_D26 (0x00000034)
|
||||
#define CONTROL_PADCONF_SDRC_D28 (0x00000038)
|
||||
#define CONTROL_PADCONF_SDRC_D30 (0x0000003C)
|
||||
#define CONTROL_PADCONF_SDRC_CLK (0x00000040)
|
||||
#define CONTROL_PADCONF_SDRC_DQS1 (0x00000044)
|
||||
#define CONTROL_PADCONF_SDRC_DQS3 (0x00000048)
|
||||
#define CONTROL_PADCONF_GPMC_A2 (0x0000004C)
|
||||
#define CONTROL_PADCONF_GPMC_A4 (0x00000050)
|
||||
#define CONTROL_PADCONF_GPMC_A6 (0x00000054)
|
||||
#define CONTROL_PADCONF_GPMC_A8 (0x00000058)
|
||||
#define CONTROL_PADCONF_GPMC_A10 (0x0000005C)
|
||||
#define CONTROL_PADCONF_GPMC_D1 (0x00000060)
|
||||
#define CONTROL_PADCONF_GPMC_D3 (0x00000064)
|
||||
#define CONTROL_PADCONF_GPMC_D5 (0x00000068)
|
||||
#define CONTROL_PADCONF_GPMC_D7 (0x0000006C)
|
||||
#define CONTROL_PADCONF_GPMC_D9 (0x00000070)
|
||||
#define CONTROL_PADCONF_GPMC_D11 (0x00000074)
|
||||
#define CONTROL_PADCONF_GPMC_D13 (0x00000078)
|
||||
#define CONTROL_PADCONF_GPMC_D15 (0x0000007C)
|
||||
#define CONTROL_PADCONF_GPMC_NCS1 (0x00000080)
|
||||
#define CONTROL_PADCONF_GPMC_NCS3 (0x00000084)
|
||||
#define CONTROL_PADCONF_GPMC_NCS5 (0x00000088)
|
||||
#define CONTROL_PADCONF_GPMC_NCS7 (0x0000008C)
|
||||
#define CONTROL_PADCONF_GPMC_NADV_ALE (0x00000090)
|
||||
#define CONTROL_PADCONF_GPMC_NWE (0x00000094)
|
||||
#define CONTROL_PADCONF_GPMC_NBE1 (0x00000098)
|
||||
#define CONTROL_PADCONF_GPMC_WAIT0 (0x0000009C)
|
||||
#define CONTROL_PADCONF_GPMC_WAIT2 (0x000000A0)
|
||||
#define CONTROL_PADCONF_DSS_PCLK (0x000000A4)
|
||||
#define CONTROL_PADCONF_DSS_VSYNC (0x000000A8)
|
||||
#define CONTROL_PADCONF_DSS_DATA0 (0x000000AC)
|
||||
#define CONTROL_PADCONF_DSS_DATA2 (0x000000B0)
|
||||
#define CONTROL_PADCONF_DSS_DATA4 (0x000000B4)
|
||||
#define CONTROL_PADCONF_DSS_DATA6 (0x000000B8)
|
||||
#define CONTROL_PADCONF_DSS_DATA8 (0x000000BC)
|
||||
#define CONTROL_PADCONF_DSS_DATA10 (0x000000C0)
|
||||
#define CONTROL_PADCONF_DSS_DATA12 (0x000000C4)
|
||||
#define CONTROL_PADCONF_DSS_DATA14 (0x000000C8)
|
||||
#define CONTROL_PADCONF_DSS_DATA16 (0x000000CC)
|
||||
#define CONTROL_PADCONF_DSS_DATA18 (0x000000D0)
|
||||
#define CONTROL_PADCONF_DSS_DATA20 (0x000000D4)
|
||||
#define CONTROL_PADCONF_DSS_DATA22 (0x000000D8)
|
||||
#define CONTROL_PADCONF_CAM_HS (0x000000DC)
|
||||
#define CONTROL_PADCONF_CAM_XCLKA (0x000000E0)
|
||||
#define CONTROL_PADCONF_CAM_FLD (0x000000E4)
|
||||
#define CONTROL_PADCONF_CAM_D1 (0x000000E8)
|
||||
#define CONTROL_PADCONF_CAM_D3 (0x000000EC)
|
||||
#define CONTROL_PADCONF_CAM_D5 (0x000000F0)
|
||||
#define CONTROL_PADCONF_CAM_D7 (0x000000F4)
|
||||
#define CONTROL_PADCONF_CAM_D9 (0x000000F8)
|
||||
#define CONTROL_PADCONF_CAM_D11 (0x000000FC)
|
||||
#define CONTROL_PADCONF_CAM_WEN (0x00000100)
|
||||
#define CONTROL_PADCONF_CSI2_DX0 (0x00000104)
|
||||
#define CONTROL_PADCONF_CSI2_DX1 (0x00000108)
|
||||
#define CONTROL_PADCONF_MCBSP2_FSX (0x0000010C)
|
||||
#define CONTROL_PADCONF_MCBSP2_DR (0x00000110)
|
||||
#define CONTROL_PADCONF_MMC1_CLK (0x00000114)
|
||||
#define CONTROL_PADCONF_MMC1_DAT0 (0x00000118)
|
||||
#define CONTROL_PADCONF_MMC1_DAT2 (0x0000011C)
|
||||
#define CONTROL_PADCONF_MMC2_CLK (0x00000128)
|
||||
#define CONTROL_PADCONF_MMC2_DAT0 (0x0000012C)
|
||||
#define CONTROL_PADCONF_MMC2_DAT2 (0x00000130)
|
||||
#define CONTROL_PADCONF_MMC2_DAT4 (0x00000134)
|
||||
#define CONTROL_PADCONF_MMC2_DAT6 (0x00000138)
|
||||
#define CONTROL_PADCONF_MCBSP3_DX (0x0000013C)
|
||||
#define CONTROL_PADCONF_MCBSP3_CLKX (0x00000140)
|
||||
#define CONTROL_PADCONF_UART2_CTS (0x00000144)
|
||||
#define CONTROL_PADCONF_UART2_TX (0x00000148)
|
||||
#define CONTROL_PADCONF_UART1_TX (0x0000014C)
|
||||
#define CONTROL_PADCONF_UART1_CTS (0x00000150)
|
||||
#define CONTROL_PADCONF_MCBSP4_CLKX (0x00000154)
|
||||
#define CONTROL_PADCONF_MCBSP4_DX (0x00000158)
|
||||
#define CONTROL_PADCONF_MCBSP1_CLKR (0x0000015C)
|
||||
#define CONTROL_PADCONF_MCBSP1_DX (0x00000160)
|
||||
#define CONTROL_PADCONF_MCBSP_CLKS (0x00000164)
|
||||
#define CONTROL_PADCONF_MCBSP1_CLKX (0x00000168)
|
||||
#define CONTROL_PADCONF_UART3_RTS_SD (0x0000016C)
|
||||
#define CONTROL_PADCONF_UART3_TX_IRTX (0x00000170)
|
||||
#define CONTROL_PADCONF_HSUSB0_STP (0x00000174)
|
||||
#define CONTROL_PADCONF_HSUSB0_NXT (0x00000178)
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA1 (0x0000017C)
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA3 (0x00000180)
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA5 (0x00000184)
|
||||
#define CONTROL_PADCONF_HSUSB0_DATA7 (0x00000188)
|
||||
#define CONTROL_PADCONF_I2C1_SDA (0x0000018C)
|
||||
#define CONTROL_PADCONF_I2C2_SDA (0x00000190)
|
||||
#define CONTROL_PADCONF_I2C3_SDA (0x00000194)
|
||||
#define CONTROL_PADCONF_MCSPI1_CLK (0x00000198)
|
||||
#define CONTROL_PADCONF_MCSPI1_SOMI (0x0000019C)
|
||||
#define CONTROL_PADCONF_MCSPI1_CS1 (0x000001A0)
|
||||
#define CONTROL_PADCONF_MCSPI1_CS3 (0x000001A4)
|
||||
#define CONTROL_PADCONF_MCSPI2_SIMO (0x000001A8)
|
||||
#define CONTROL_PADCONF_MCSPI2_CS0 (0x000001AC)
|
||||
#define CONTROL_PADCONF_SYS_NIRQ (0x000001B0)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD0 (0x000001B4)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD2 (0x000001B8)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD4 (0x000001BC)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD6 (0x000001C0)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD8 (0x000001C4)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD10 (0x000001C8)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD12 (0x000001CC)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD14 (0x000001D0)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD16 (0x000001D4)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD18 (0x000001D8)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD20 (0x000001DC)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD22 (0x000001E0)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD24 (0x000001E4)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD26 (0x000001E8)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD28 (0x000001EC)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD30 (0x000001F0)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD32 (0x000001F4)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD34 (0x000001F8)
|
||||
#define CONTROL_PADCONF_SAD2D_MCAD36 (0x000001FC)
|
||||
#define CONTROL_PADCONF_SAD2D_NRESPWRON (0x00000200)
|
||||
#define CONTROL_PADCONF_SAD2D_ARMNIRQ (0x00000204)
|
||||
#define CONTROL_PADCONF_SAD2D_SPINT (0x00000208)
|
||||
#define CONTROL_PADCONF_SAD2D_DMAREQ0 (0x0000020C)
|
||||
#define CONTROL_PADCONF_SAD2D_DMAREQ2 (0x00000210)
|
||||
#define CONTROL_PADCONF_SAD2D_NTRST (0x00000214)
|
||||
#define CONTROL_PADCONF_SAD2D_TDO (0x00000218)
|
||||
#define CONTROL_PADCONF_SAD2D_TCK (0x0000021C)
|
||||
#define CONTROL_PADCONF_SAD2D_MSTDBY (0x00000220)
|
||||
#define CONTROL_PADCONF_SAD2D_IDLEACK (0x00000224)
|
||||
#define CONTROL_PADCONF_SAD2D_SWRITE (0x00000228)
|
||||
#define CONTROL_PADCONF_SAD2D_SREAD (0x0000022C)
|
||||
#define CONTROL_PADCONF_SAD2D_SBUSFLAG (0x00000230)
|
||||
#define CONTROL_PADCONF_SDRC_CKE1 (0x00000234)
|
||||
#define CONTROL_PADCONF_SDRC_BA0 (0x00000570)
|
||||
#define CONTROL_PADCONF_SDRC_A0 (0x00000574)
|
||||
#define CONTROL_PADCONF_SDRC_A2 (0x00000578)
|
||||
#define CONTROL_PADCONF_SDRC_A4 (0x0000057C)
|
||||
#define CONTROL_PADCONF_SDRC_A6 (0x00000580)
|
||||
#define CONTROL_PADCONF_SDRC_A8 (0x00000584)
|
||||
#define CONTROL_PADCONF_SDRC_A10 (0x00000588)
|
||||
#define CONTROL_PADCONF_SDRC_A12 (0x0000058C)
|
||||
#define CONTROL_PADCONF_SDRC_A14 (0x00000590)
|
||||
#define CONTROL_PADCONF_SDRC_NCS1 (0x00000594)
|
||||
#define CONTROL_PADCONF_SDRC_NRAS (0x00000598)
|
||||
#define CONTROL_PADCONF_SDRC_NWE (0x0000059C)
|
||||
#define CONTROL_PADCONF_SDRC_DM1 (0x000005A0)
|
||||
#define CONTROL_PADCONF_SDRC_DM3 (0x000005A4)
|
||||
#define CONTROL_PADCONF_ETK_CLK (0x000005A8)
|
||||
#define CONTROL_PADCONF_ETK_D0 (0x000005AC)
|
||||
#define CONTROL_PADCONF_ETK_D2 (0x000005B0)
|
||||
#define CONTROL_PADCONF_ETK_D4 (0x000005B4)
|
||||
#define CONTROL_PADCONF_ETK_D6 (0x000005B8)
|
||||
#define CONTROL_PADCONF_ETK_D8 (0x000005BC)
|
||||
#define CONTROL_PADCONF_ETK_D10 (0x000005C0)
|
||||
#define CONTROL_PADCONF_ETK_D12 (0x000005C4)
|
||||
#define CONTROL_PADCONF_ETK_D14 (0x000005C8)
|
||||
|
||||
/* conf pin descriptions (am335x) */
|
||||
#define CONTROL_CONF_GPMC_AD0 (0x00000800)
|
||||
#define CONTROL_CONF_GPMC_AD1 (0x00000804)
|
||||
#define CONTROL_CONF_GPMC_AD2 (0x00000808)
|
||||
#define CONTROL_CONF_GPMC_AD3 (0x0000080C)
|
||||
#define CONTROL_CONF_GPMC_AD4 (0x00000810)
|
||||
#define CONTROL_CONF_GPMC_AD5 (0x00000814)
|
||||
#define CONTROL_CONF_GPMC_AD6 (0x00000818)
|
||||
#define CONTROL_CONF_GPMC_AD7 (0x0000081C)
|
||||
#define CONTROL_CONF_GPMC_AD8 (0x00000820)
|
||||
#define CONTROL_CONF_GPMC_AD9 (0x00000824)
|
||||
#define CONTROL_CONF_GPMC_AD10 (0x00000828)
|
||||
#define CONTROL_CONF_GPMC_AD11 (0x0000082C)
|
||||
#define CONTROL_CONF_GPMC_AD12 (0x00000830)
|
||||
#define CONTROL_CONF_GPMC_AD13 (0x00000834)
|
||||
#define CONTROL_CONF_GPMC_AD14 (0x00000838)
|
||||
#define CONTROL_CONF_GPMC_AD15 (0x0000083C)
|
||||
#define CONTROL_CONF_GPMC_A0 (0x00000840)
|
||||
#define CONTROL_CONF_GPMC_A1 (0x00000844)
|
||||
#define CONTROL_CONF_GPMC_A2 (0x00000848)
|
||||
#define CONTROL_CONF_GPMC_A3 (0x0000084C)
|
||||
#define CONTROL_CONF_GPMC_A4 (0x00000850)
|
||||
#define CONTROL_CONF_GPMC_A5 (0x00000854)
|
||||
#define CONTROL_CONF_GPMC_A6 (0x00000858)
|
||||
#define CONTROL_CONF_GPMC_A7 (0x0000085C)
|
||||
#define CONTROL_CONF_GPMC_A8 (0x00000860)
|
||||
#define CONTROL_CONF_GPMC_A9 (0x00000864)
|
||||
#define CONTROL_CONF_GPMC_A10 (0x00000868)
|
||||
#define CONTROL_CONF_GPMC_A11 (0x0000086C)
|
||||
#define CONTROL_CONF_GPMC_WAIT0 (0x00000870)
|
||||
#define CONTROL_CONF_GPMC_WPN (0x00000874)
|
||||
#define CONTROL_CONF_GPMC_BEN1 (0x00000878)
|
||||
#define CONTROL_CONF_GPMC_CSN0 (0x0000087C)
|
||||
#define CONTROL_CONF_GPMC_CSN1 (0x00000880)
|
||||
#define CONTROL_CONF_GPMC_CSN2 (0x00000884)
|
||||
#define CONTROL_CONF_GPMC_CSN3 (0x00000888)
|
||||
#define CONTROL_CONF_GPMC_CLK (0x0000088C)
|
||||
#define CONTROL_CONF_GPMC_ADVN_ALE (0x00000890)
|
||||
#define CONTROL_CONF_GPMC_OEN_REN (0x00000894)
|
||||
#define CONTROL_CONF_GPMC_WEN (0x00000898)
|
||||
#define CONTROL_CONF_GPMC_BEN0_CLE (0x0000089C)
|
||||
#define CONTROL_CONF_LCD_DATA0 (0x000008A0)
|
||||
#define CONTROL_CONF_LCD_DATA1 (0x000008A4)
|
||||
#define CONTROL_CONF_LCD_DATA2 (0x000008A8)
|
||||
#define CONTROL_CONF_LCD_DATA3 (0x000008AC)
|
||||
#define CONTROL_CONF_LCD_DATA4 (0x000008B0)
|
||||
#define CONTROL_CONF_LCD_DATA5 (0x000008B4)
|
||||
#define CONTROL_CONF_LCD_DATA6 (0x000008B8)
|
||||
#define CONTROL_CONF_LCD_DATA7 (0x000008BC)
|
||||
#define CONTROL_CONF_LCD_DATA8 (0x000008C0)
|
||||
#define CONTROL_CONF_LCD_DATA9 (0x000008C4)
|
||||
#define CONTROL_CONF_LCD_DATA10 (0x000008C8)
|
||||
#define CONTROL_CONF_LCD_DATA11 (0x000008CC)
|
||||
#define CONTROL_CONF_LCD_DATA12 (0x000008D0)
|
||||
#define CONTROL_CONF_LCD_DATA13 (0x000008D4)
|
||||
#define CONTROL_CONF_LCD_DATA14 (0x000008D8)
|
||||
#define CONTROL_CONF_LCD_DATA15 (0x000008DC)
|
||||
#define CONTROL_CONF_LCD_VSYNC (0x000008E0)
|
||||
#define CONTROL_CONF_LCD_HSYNC (0x000008E4)
|
||||
#define CONTROL_CONF_LCD_PCLK (0x000008E8)
|
||||
#define CONTROL_CONF_LCD_AC_BIAS_EN (0x000008EC)
|
||||
#define CONTROL_CONF_MMC0_DAT3 (0x000008F0)
|
||||
#define CONTROL_CONF_MMC0_DAT2 (0x000008F4)
|
||||
#define CONTROL_CONF_MMC0_DAT1 (0x000008F8)
|
||||
#define CONTROL_CONF_MMC0_DAT0 (0x000008FC)
|
||||
#define CONTROL_CONF_MMC0_CLK (0x00000900)
|
||||
#define CONTROL_CONF_MMC0_CMD (0x00000904)
|
||||
#define CONTROL_CONF_MII1_COL (0x00000908)
|
||||
#define CONTROL_CONF_MII1_CRS (0x0000090C)
|
||||
#define CONTROL_CONF_MII1_RX_ER (0x00000910)
|
||||
#define CONTROL_CONF_MII1_TX_EN (0x00000914)
|
||||
#define CONTROL_CONF_MII1_RX_DV (0x00000918)
|
||||
#define CONTROL_CONF_MII1_TXD3 (0x0000091C)
|
||||
#define CONTROL_CONF_MII1_TXD2 (0x00000920)
|
||||
#define CONTROL_CONF_MII1_TXD1 (0x00000924)
|
||||
#define CONTROL_CONF_MII1_TXD0 (0x00000928)
|
||||
#define CONTROL_CONF_MII1_TX_CLK (0x0000092C)
|
||||
#define CONTROL_CONF_MII1_RX_CLK (0x00000930)
|
||||
#define CONTROL_CONF_MII1_RXD3 (0x00000934)
|
||||
#define CONTROL_CONF_MII1_RXD2 (0x00000938)
|
||||
#define CONTROL_CONF_MII1_RXD1 (0x0000093C)
|
||||
#define CONTROL_CONF_MII1_RXD0 (0x00000940)
|
||||
#define CONTROL_CONF_RMII1_REF_CLK (0x00000944)
|
||||
#define CONTROL_CONF_MDIO (0x00000948)
|
||||
#define CONTROL_CONF_MDC (0x0000094C)
|
||||
#define CONTROL_CONF_SPI0_SCLK (0x00000950)
|
||||
#define CONTROL_CONF_SPI0_D0 (0x00000954)
|
||||
#define CONTROL_CONF_SPI0_D1 (0x00000958)
|
||||
#define CONTROL_CONF_SPI0_CS0 (0x0000095C)
|
||||
#define CONTROL_CONF_SPI0_CS1 (0x00000960)
|
||||
#define CONTROL_CONF_ECAP0_IN_PWM0_OUT (0x00000964)
|
||||
#define CONTROL_CONF_UART0_CTSN (0x00000968)
|
||||
#define CONTROL_CONF_UART0_RTSN (0x0000096C)
|
||||
#define CONTROL_CONF_UART0_RXD (0x00000970)
|
||||
#define CONTROL_CONF_UART0_TXD (0x00000974)
|
||||
#define CONTROL_CONF_UART1_CTSN (0x00000978)
|
||||
#define CONTROL_CONF_UART1_RTSN (0x0000097C)
|
||||
#define CONTROL_CONF_UART1_RXD (0x00000980)
|
||||
#define CONTROL_CONF_UART1_TXD (0x00000984)
|
||||
#define CONTROL_CONF_I2C0_SDA (0x00000988)
|
||||
#define CONTROL_CONF_I2C0_SCL (0x0000098C)
|
||||
#define CONTROL_CONF_MCASP0_ACLKX (0x00000990)
|
||||
#define CONTROL_CONF_MCASP0_FSX (0x00000994)
|
||||
#define CONTROL_CONF_MCASP0_AXR0 (0x00000998)
|
||||
#define CONTROL_CONF_MCASP0_AHCLKR (0x0000099C)
|
||||
#define CONTROL_CONF_MCASP0_ACLKR (0x000009A0)
|
||||
#define CONTROL_CONF_MCASP0_FSR (0x000009A4)
|
||||
#define CONTROL_CONF_MCASP0_AXR1 (0x000009A8)
|
||||
#define CONTROL_CONF_MCASP0_AHCLKX (0x000009AC)
|
||||
#define CONTROL_CONF_XDMA_EVENT_INTR0 (0x000009B0)
|
||||
#define CONTROL_CONF_XDMA_EVENT_INTR1 (0x000009B4)
|
||||
#define CONTROL_CONF_WARMRSTN (0x000009B8)
|
||||
#define CONTROL_CONF_NNMI (0x000009C0)
|
||||
#define CONTROL_CONF_TMS (0x000009D0)
|
||||
#define CONTROL_CONF_TDI (0x000009D4)
|
||||
#define CONTROL_CONF_TDO (0x000009D8)
|
||||
#define CONTROL_CONF_TCK (0x000009DC)
|
||||
#define CONTROL_CONF_TRSTN (0x000009E0)
|
||||
#define CONTROL_CONF_EMU0 (0x000009E4)
|
||||
#define CONTROL_CONF_EMU1 (0x000009E8)
|
||||
#define CONTROL_CONF_RTC_PWRONRSTN (0x000009F8)
|
||||
#define CONTROL_CONF_PMIC_POWER_EN (0x000009FC)
|
||||
#define CONTROL_CONF_EXT_WAKEUP (0x00000A00)
|
||||
#define CONTROL_CONF_RTC_KALDO_ENN (0x00000A04)
|
||||
#define CONTROL_CONF_USB0_DRVVBUS (0x00000A1C)
|
||||
#define CONTROL_CONF_USB1_DRVVBUS (0x00000A34)
|
||||
|
||||
#define CONTROL_CONF_SLEWCTRL (1<<6)
|
||||
#define CONTROL_CONF_RXACTIVE (1<<5)
|
||||
#define CONTROL_CONF_PUTYPESEL (1<<4)
|
||||
#define CONTROL_CONF_PUDEN (1<<3)
|
||||
#define CONTROL_CONF_MUXMODE(X) (X&0x7)
|
||||
|
||||
#endif /* __PADCONF_H__ */
|
||||
|
|
@ -43,6 +43,10 @@
|
|||
#define USE_MEMSET 1 /* write char to a given memory area */
|
||||
#define USE_RUNCTL 1 /* control stop flags of a process */
|
||||
|
||||
#if defined(__arm__)
|
||||
#define USE_PADCONF 1 /* configure pinmux */
|
||||
#endif /* __arm__ */
|
||||
|
||||
/* This section contains defines for valuable system resources that are used
|
||||
* by device drivers. The number of elements of the vectors is determined by
|
||||
* the maximum needed by any given driver. The number of interrupt hooks may
|
||||
|
|
|
|||
|
|
@ -248,6 +248,11 @@ void system_init(void)
|
|||
map(SYS_CPROF, do_cprofile); /* get/reset call profiling data */
|
||||
map(SYS_PROFBUF, do_profbuf); /* announce locations to kernel */
|
||||
|
||||
/* arm-specific. */
|
||||
#if defined(__arm__)
|
||||
map(SYS_PADCONF, do_padconf); /* configure pinmux */
|
||||
#endif
|
||||
|
||||
/* i386-specific. */
|
||||
#if defined(__i386__)
|
||||
map(SYS_READBIOS, do_readbios); /* read from BIOS locations */
|
||||
|
|
|
|||
|
|
@ -208,5 +208,10 @@ int do_statectl(struct proc * caller, message *m_ptr);
|
|||
#define do_statectl NULL
|
||||
#endif
|
||||
|
||||
int do_padconf(struct proc * caller, message *m_ptr);
|
||||
#if ! USE_PADCONF
|
||||
#define do_padconf NULL
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_H */
|
||||
|
||||
|
|
|
|||
|
|
@ -40,6 +40,11 @@ SRCS+= \
|
|||
do_schedctl.c \
|
||||
do_statectl.c
|
||||
|
||||
.if ${MACHINE_ARCH} == "earm"
|
||||
SRCS+= \
|
||||
do_padconf.c
|
||||
.endif
|
||||
|
||||
.if ${MACHINE_ARCH} == "i386"
|
||||
SRCS+= \
|
||||
do_devio.c \
|
||||
|
|
|
|||
20
kernel/system/do_padconf.c
Normal file
20
kernel/system/do_padconf.c
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
#include "kernel/system.h"
|
||||
#include <minix/endpoint.h>
|
||||
|
||||
#if USE_PADCONF
|
||||
|
||||
/* get arch specific arch_padconf_set() */
|
||||
#if defined(AM335X) || defined(DM37XX)
|
||||
#include "omap_padconf.h"
|
||||
#endif
|
||||
|
||||
/*===========================================================================*
|
||||
* do_padconf *
|
||||
*===========================================================================*/
|
||||
int do_padconf(struct proc *caller_ptr, message *m_ptr)
|
||||
{
|
||||
return arch_padconf_set(m_ptr->PADCONF_PADCONF, m_ptr->PADCONF_MASK,
|
||||
m_ptr->PADCONF_VALUE);
|
||||
}
|
||||
|
||||
#endif /* USE_PADCONF */
|
||||
|
|
@ -54,7 +54,7 @@ SUBDIR += libvassert libhgfs libvboxfs libvirtio
|
|||
.endif
|
||||
|
||||
.if (${MACHINE_ARCH} == "earm")
|
||||
SUBDIR += libclkconf libgpio libi2cdriver libpadconf
|
||||
SUBDIR += libclkconf libgpio libi2cdriver
|
||||
.endif
|
||||
|
||||
.if (${MKRUMP} != "no")
|
||||
|
|
|
|||
|
|
@ -1,12 +0,0 @@
|
|||
# Makefile for libpadconf
|
||||
|
||||
CPPFLAGS+= -D_SYSTEM
|
||||
|
||||
LIB= padconf
|
||||
|
||||
SRCS= \
|
||||
padconf.c
|
||||
|
||||
WARNS?= 5
|
||||
|
||||
.include <bsd.lib.mk>
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
/* kernel headers */
|
||||
#include <minix/syslib.h>
|
||||
#include <minix/drvlib.h>
|
||||
#include <minix/log.h>
|
||||
#include <minix/padconf.h>
|
||||
#include <minix/mmio.h>
|
||||
|
||||
/* system headers */
|
||||
#include <sys/mman.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
/* usr headers */
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
#include <errno.h>
|
||||
#include <assert.h>
|
||||
|
||||
/* local headers */
|
||||
|
||||
/* used for logging */
|
||||
static struct log log = {
|
||||
.name = "omap_padconf",
|
||||
.log_level = LEVEL_INFO,
|
||||
.log_func = default_log
|
||||
};
|
||||
|
||||
static u32_t base = 0;
|
||||
static u32_t use_count = 0;
|
||||
|
||||
int
|
||||
padconf_init()
|
||||
{
|
||||
struct minix_mem_range mr;
|
||||
|
||||
use_count++;
|
||||
|
||||
if (base != 0) {
|
||||
/* when used in a library we can't guaranty we only call this
|
||||
* method once */
|
||||
log_trace(&log, "Called %d times\n", use_count);
|
||||
return OK;
|
||||
}
|
||||
|
||||
mr.mr_base = PADCONF_REGISTERS_BASE;
|
||||
mr.mr_limit = PADCONF_REGISTERS_BASE + 0x1000;
|
||||
|
||||
if (sys_privctl(SELF, SYS_PRIV_ADD_MEM, &mr) != 0) {
|
||||
log_warn(&log, "Unable to request permission to map memory\n");
|
||||
return EPERM;
|
||||
}
|
||||
|
||||
base =
|
||||
(uint32_t) vm_map_phys(SELF, (void *) PADCONF_REGISTERS_BASE,
|
||||
0x1000);
|
||||
|
||||
if (base == (uint32_t) MAP_FAILED) {
|
||||
log_warn(&log, "Unable to map GPIO memory\n");
|
||||
return EPERM;
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
int
|
||||
padconf_set(u32_t padconf, u32_t mask, u32_t value)
|
||||
{
|
||||
assert(padconf <= CONTROL_CONF_USB1_DRVVBUS);
|
||||
set32(base + padconf, mask, value);
|
||||
return OK;
|
||||
}
|
||||
|
||||
int
|
||||
padconf_release()
|
||||
{
|
||||
assert(use_count > 0);
|
||||
use_count--;
|
||||
|
||||
if (use_count == 0) {
|
||||
vm_unmap_phys(SELF, (void *) base, 0x1000);
|
||||
}
|
||||
base = 0;
|
||||
return OK;
|
||||
}
|
||||
|
|
@ -49,6 +49,7 @@ SRCS+= \
|
|||
sys_kill.c \
|
||||
sys_mcontext.c \
|
||||
sys_memset.c \
|
||||
sys_padconf.c \
|
||||
sys_physcopy.c \
|
||||
sys_privctl.c \
|
||||
sys_profbuf.c \
|
||||
|
|
|
|||
14
lib/libsys/sys_padconf.c
Normal file
14
lib/libsys/sys_padconf.c
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#include <stdint.h>
|
||||
|
||||
#include "syslib.h"
|
||||
|
||||
int sys_padconf(u32_t padconf, u32_t mask, u32_t value)
|
||||
{
|
||||
message m;
|
||||
|
||||
m.PADCONF_PADCONF = padconf;
|
||||
m.PADCONF_MASK = mask;
|
||||
m.PADCONF_VALUE = value;
|
||||
|
||||
return(_kernel_call(SYS_PADCONF, &m));
|
||||
}
|
||||
Loading…
Reference in a new issue