mmc:development
* let busy loops timeout. * Start using interrupt handlers. * Allocate the ramdisk only when used. Change-Id: Ie08d66eefef3c8cd3ee16c04f74a9a50cc12b021
This commit is contained in:
Kees Jongenburger
Kees Jongenburger
parent
c31c70743a
commit
3de9b14567
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@ -6,6 +6,8 @@
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#include <minix/driver.h>
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#include <minix/blockdriver.h>
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#include <minix/drvlib.h>
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#include <minix/minlib.h>
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/* system headers */
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#include <sys/ioc_disk.h> /* disk IOCTL's */
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@ -24,25 +26,13 @@
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/* used for logging */
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static struct mmclog log = {
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.name = "mmc_block",
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.log_level = LEVEL_DEBUG,
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.log_level = LEVEL_INFO,
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.log_func = default_log
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};
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/* holding the current host controller */
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static struct mmc_host host;
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/*@TODO REMOVE THIS */
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void
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read_tsc_64(u64_t * t)
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{
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}
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u32_t
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tsc_64_to_micros(u64_t tsc)
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{
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return 0;
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}
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#define SUB_PER_DRIVE (NR_PARTITIONS * NR_PARTITIONS)
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#define NR_SUBDEVS (MAX_DRIVES * SUB_PER_DRIVE)
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@ -70,12 +60,18 @@ static void sef_local_startup();
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static int block_system_event_cb(int type, sef_init_info_t * info);
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static void block_signal_handler_cb(int signo);
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static int apply_env();
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void
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bdr_alarm(clock_t stamp)
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{
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mmc_log_debug(&log, "alarm %d\n", stamp);
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}
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static int apply_env();
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static void hw_intr(unsigned int irqs);
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#if 0
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/* set the global logging level */
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static void set_log_level(int level);
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#endif
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/* Entry points for the BLOCK driver. */
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static struct blockdriver mmc_driver = {
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@ -87,20 +83,28 @@ static struct blockdriver mmc_driver = {
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NULL, /* no need to clean up (yet) */
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block_part, /* return partition information */
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NULL, /* no geometry */
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NULL, /* no interrupt processing */
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NULL, /* no alarm processing */
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hw_intr, /* left over interrupts */
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bdr_alarm, /* no alarm processing */
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NULL, /* no processing of other messages */
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NULL /* no threading support */
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};
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static void
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hw_intr(unsigned int irqs)
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{
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mmc_log_debug(&log, "Hardware inter left over\n");
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host.hw_intr(irqs);
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}
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static int
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apply_env()
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{
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long v;
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/* apply the env setting passed to this driver parameters accepted
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* log_level=[0-4] (NONE,WARNING,INFO,DEBUG,TRACE) instance=[0-3]
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* log_level=[0-4] (NONE,WARN,INFO,DEBUG,TRACE) instance=[0-3]
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* instance/bus number to use for this driver Passing these arguments
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* is done when starting the driver using the service command in the
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* following way service up /sbin/mmc -args "log_level=2 instance=1
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* following way service up /sbin/mmc -args "log_level=2 instance=1
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* driver=dummy" -dev /dev/c2d0 */
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char driver[16];
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memset(driver, '\0', 16);
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@ -115,10 +119,6 @@ apply_env()
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} else {
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mmc_log_warn(&log, "Unknown driver %s\n", driver);
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}
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#if 0
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long v;
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/* The following code(env_parse) uses strtol.c and needs __aeabi_idiv */
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/* @TODO: re-enable this function when __aeabi_idiv will be present */
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/* Initialize the verbosity level. */
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v = 0;
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if (env_parse("log_level", "d", 0, &v, LEVEL_NONE,
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@ -133,7 +133,6 @@ apply_env()
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mmc_log_warn(&log, "Failed to set mmc instance to %d\n", v);
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return -1; /* NOT OK */
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}
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#endif
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return OK;
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}
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@ -185,27 +184,27 @@ block_open(dev_t minor, int access)
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partition(&mmc_driver, 0 /* first card on bus */ , P_PRIMARY,
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0 /* atapi device?? */ );
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mmc_log_debug(&log, "descr \toffset(bytes) size(bytes)\n", minor);
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mmc_log_trace(&log, "descr \toffset(bytes) size(bytes)\n", minor);
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mmc_log_debug(&log, "disk %d\t0x%016llx 0x%016llx\n", i,
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mmc_log_trace(&log, "disk %d\t0x%016llx 0x%016llx\n", i,
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slot->card.part[0].dv_base, slot->card.part[0].dv_size);
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for (i = 1; i < 5; i++) {
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if (slot->card.part[i].dv_size == 0)
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continue;
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part_count++;
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mmc_log_debug(&log, "part %d\t0x%016llx 0x%016llx\n", i,
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mmc_log_trace(&log, "part %d\t0x%016llx 0x%016llx\n", i,
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slot->card.part[i].dv_base, slot->card.part[i].dv_size);
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for (j = 0; j < 4; j++) {
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if (slot->card.subpart[(i - 1) * 4 + j].dv_size == 0)
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continue;
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sub_part_count++;
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mmc_log_debug(&log,
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mmc_log_trace(&log,
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" sub %d/%d\t0x%016llx 0x%016llx\n", i, j,
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slot->card.subpart[(i - 1) * 4 + j].dv_base,
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slot->card.subpart[(i - 1) * 4 + j].dv_size);
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}
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}
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mmc_log_info(&log, "Found %d partitions and %d sub partitions\n",
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mmc_log_debug(&log, "Found %d partitions and %d sub partitions\n",
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part_count, sub_part_count);
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slot->card.open_ct++;
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assert(slot->card.open_ct == 1);
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@ -312,7 +311,7 @@ block_transfer(dev_t minor, /* minor device number */
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/* Unknown device */
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return ENXIO;
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}
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mmc_log_trace(&log, "I/O %d %s 0x%llx\n", minor,
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mmc_log_trace(&log, "I/O on minor(%d) %s at 0x%016llx\n", minor,
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(do_write) ? "Write" : "Read", position);
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slot = get_slot(minor);
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@ -636,20 +635,18 @@ get_slot(dev_t minor)
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}
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}
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#if 0
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static void
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set_log_level(int level)
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{
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if (level < 0 || level >= 4) {
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return;
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}
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mmc_log_debug(&log, "Setting verbosity level to %d\n", level);
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mmc_log_info(&log, "Setting verbosity level to %d\n", level);
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log.log_level = level;
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if (host.set_log_level) {
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host.set_log_level(level);
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}
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}
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#endif
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int
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main(int argc, char **argv)
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@ -657,7 +654,6 @@ main(int argc, char **argv)
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/* Set and apply the environment */
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env_setargs(argc, argv);
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sef_local_startup();
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blockdriver_task(&mmc_driver);
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return EXIT_SUCCESS;
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@ -117,6 +117,9 @@ struct mmc_host
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/* Release the card */
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int (*card_release) (struct sd_card * card);
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/* Additional hardware interrupts */
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void (*hw_intr) (unsigned int irqs);
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/* read count blocks into existing buf */
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int (*read) (struct sd_card * card,
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uint32_t blknr, uint32_t count, unsigned char *buf);
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@ -1,11 +1,13 @@
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/* kernel headers */
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#include <minix/blockdriver.h>
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#include <minix/minlib.h>
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/* usr headers */
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include <assert.h>
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#include <unistd.h>
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/* local headers */
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#include "mmclog.h"
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@ -17,14 +19,14 @@
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*/
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static struct mmclog log = {
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.name = "mmc_host_memory",
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.log_level = LEVEL_TRACE,
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.log_level = LEVEL_INFO,
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.log_func = default_log
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};
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/* This is currently a dummy driver using an in-memory structure */
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#define DUMMY_SIZE_IN_BLOCKS 0xFFFu
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#define DUMMY_SIZE_IN_BLOCKS 0xFFFFFu
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#define DUMMY_BLOCK_SIZE 512
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static char dummy_data[DUMMY_BLOCK_SIZE * DUMMY_SIZE_IN_BLOCKS];
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static char *dummy_data = NULL;
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static struct sd_card *
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init_dummy_sdcard(struct sd_slot *slot)
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@ -35,6 +37,13 @@ init_dummy_sdcard(struct sd_slot *slot)
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assert(slot != NULL);
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mmc_log_info(&log, "Using a dummy card \n");
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if (dummy_data == NULL) {
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dummy_data = malloc(DUMMY_BLOCK_SIZE * DUMMY_SIZE_IN_BLOCKS);
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if (dummy_data == NULL) {
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panic
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("Failed to allocate data for dummy mmc driver\n");
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}
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}
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card = &slot->card;
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memset(card, 0, sizeof(struct sd_card));
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@ -2,7 +2,9 @@
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#include <minix/blockdriver.h>
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#include <minix/com.h>
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#include <minix/vm.h>
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#include <minix/spin.h>
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#include <sys/mman.h>
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#include <sys/time.h>
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/* usr headers */
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#include <assert.h>
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@ -12,6 +14,7 @@
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#include <string.h>
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#include <inttypes.h>
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#include <limits.h>
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#include <unistd.h>
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/* local headers */
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#include "mmclog.h"
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@ -25,6 +28,14 @@
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/* omap /hardware related */
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#include "omap_mmc.h"
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#define USE_INTR
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#ifdef USE_INTR
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static int hook_id = 1;
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#define OMAP3_MMC1_IRQ 83 /* MMC/SD module 1 */
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#endif
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#define SANE_TIMEOUT 500000 /* 500 MS */
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/*
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* Define a structure to be used for logging
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*/
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@ -38,14 +49,14 @@ static struct mmclog log = {
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#define BIT(x)(0x1 << x)
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/* Write a uint32_t value to a memory address. */
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inline void
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static inline void
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write32(uint32_t address, uint32_t value)
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{
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REG(address) = value;
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}
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/* Read an uint32_t from a memory address */
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inline uint32_t
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static inline uint32_t
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read32(uint32_t address)
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{
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@ -53,7 +64,7 @@ read32(uint32_t address)
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}
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/* Set a 32 bits value depending on a mask */
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inline void
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static inline void
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set32(uint32_t address, uint32_t mask, uint32_t value)
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{
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uint32_t val;
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@ -75,13 +86,11 @@ static uint32_t base_address;
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int
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mmchs_init(uint32_t instance)
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{
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int counter;
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uint32_t value;
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counter = 0;
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value = 0;
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struct minix_mem_range mr;
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spin_t spin;
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mr.mr_base = MMCHS1_REG_BASE;
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mr.mr_limit = MMCHS1_REG_BASE + 0x400;
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@ -106,11 +115,14 @@ mmchs_init(uint32_t instance)
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MMCHS_SD_SYSCONFIG_SOFTRESET);
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/* Read sysstatus to know when it's done */
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spin_init(&spin, SANE_TIMEOUT);
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while (!(read32(base_address + MMCHS_SD_SYSSTATUS)
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& MMCHS_SD_SYSSTATUS_RESETDONE)) {
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/* TODO:Add proper delay and escape route */
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counter++;
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if (spin_check(&spin) == FALSE) {
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mmc_log_warn(&log, "mmc init timeout\n");
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return 1;
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}
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}
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/* Set SD default capabilities */
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@ -164,12 +176,14 @@ mmchs_init(uint32_t instance)
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set32(base_address + MMCHS_SD_HCTL, MMCHS_SD_HCTL_SDBP,
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MMCHS_SD_HCTL_SDBP_ON);
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/* TODO: Add padconf stuff here as documented in the TRM */
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// /* TODO: Add padconf/pinmux stuff here as documented in the TRM */
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spin_init(&spin, SANE_TIMEOUT);
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while ((read32(base_address + MMCHS_SD_HCTL) & MMCHS_SD_HCTL_SDBP)
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!= MMCHS_SD_HCTL_SDBP_ON) {
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/* TODO:Add proper delay and escape route */
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counter++;
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if (spin_check(&spin) == FALSE) {
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mmc_log_warn(&log, "mmc init timeout SDBP not set\n");
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return 1;
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}
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}
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/* Enable internal clock and clock to the card */
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@ -177,16 +191,23 @@ mmchs_init(uint32_t instance)
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MMCHS_SD_SYSCTL_ICE_EN);
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// @TODO Fix external clock enable , this one is very slow
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// but we first need faster context switching
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//set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CLKD,
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// (0x20 << 6));
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set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CLKD,
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(0x3ff << 6));
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(0x5 << 6));
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set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_CEN,
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MMCHS_SD_SYSCTL_CEN_EN);
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counter = 0;
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spin_init(&spin, SANE_TIMEOUT);
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while ((read32(base_address + MMCHS_SD_SYSCTL) & MMCHS_SD_SYSCTL_ICS)
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!= MMCHS_SD_SYSCTL_ICS_STABLE) {
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/* TODO:Add proper delay and escape route */
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counter++;
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if (spin_check(&spin) == FALSE) {
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mmc_log_warn(&log, "clock not stable\n");
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return 1;
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}
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}
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/*
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@ -216,7 +237,7 @@ mmchs_init(uint32_t instance)
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/* command 0 , type other commands not response etc) */
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write32(base_address + MMCHS_SD_CMD, 0x00);
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counter = 0;
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spin_init(&spin, SANE_TIMEOUT);
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while ((read32(base_address + MMCHS_SD_STAT) & MMCHS_SD_STAT_CC)
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!= MMCHS_SD_STAT_CC_RAISED) {
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if (read32(base_address + MMCHS_SD_STAT) & 0x8000) {
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@ -225,7 +246,12 @@ mmchs_init(uint32_t instance)
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read32(base_address + MMCHS_SD_STAT));
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return 1;
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}
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counter++;
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if (spin_check(&spin) == FALSE) {
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mmc_log_warn(&log,
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"Interrupt not raised during init\n");
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return 1;
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}
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}
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/* clear the cc interrupt status */
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@ -238,41 +264,151 @@ mmchs_init(uint32_t instance)
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set32(base_address + MMCHS_SD_CON, MMCHS_SD_CON_INIT,
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MMCHS_SD_CON_INIT_NOINIT);
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/* Set timeout */
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set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_DTO,
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MMCHS_SD_SYSCTL_DTO_2POW27);
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/* Clean the MMCHS_SD_STAT register */
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write32(base_address + MMCHS_SD_STAT, 0xffffffffu);
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#ifdef USE_INTR
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hook_id = 1;
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if (sys_irqsetpolicy(OMAP3_MMC1_IRQ, 0, &hook_id) != OK) {
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printf("mmc: couldn't set IRQ policy %d\n", OMAP3_MMC1_IRQ);
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return 1;
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}
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/* enable signaling from MMC controller towards interrupt controller */
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write32(base_address + MMCHS_SD_ISE, 0xffffffffu);
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#endif
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return 0;
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}
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static void
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mmchs_hw_intr(unsigned int irqs)
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{
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mmc_log_warn(&log, "Hardware interrupt left over\n");
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#ifdef USE_INTR
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if (sys_irqenable(&hook_id) != OK)
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printf("couldn't re-enable interrupt \n");
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#endif
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/* Leftover interrupt(s) received; ack it/them. */
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}
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/*===========================================================================*
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* w_intr_wait *
|
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*===========================================================================*/
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static int
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intr_wait(int mask)
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{
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long v;
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#ifdef USE_INTR
|
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if (sys_irqenable(&hook_id) != OK)
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printf("Failed to enable irqenable irq\n");
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/* Wait for a task completion interrupt. */
|
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message m;
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int ipc_status;
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int ticks = SANE_TIMEOUT * sys_hz() / 1000000;
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|
||||
if (ticks <= 0) ticks =1;
|
||||
while (1) {
|
||||
int rr;
|
||||
sys_setalarm(ticks, 0);
|
||||
if ((rr = driver_receive(ANY, &m, &ipc_status)) != OK) {
|
||||
panic("driver_receive failed: %d", rr);
|
||||
};
|
||||
if (is_ipc_notify(ipc_status)) {
|
||||
switch (_ENDPOINT_P(m.m_source)) {
|
||||
case CLOCK:
|
||||
/* Timeout. */
|
||||
// w_timeout(); /* a.o. set w_status */
|
||||
mmc_log_warn(&log, "TIMEOUT\n");
|
||||
return 1;
|
||||
break;
|
||||
case HARDWARE:
|
||||
v = read32(base_address + MMCHS_SD_STAT);
|
||||
if (v & mask) {
|
||||
sys_setalarm(0, 0);
|
||||
return 0;
|
||||
} else if (v & (1 << 15)){
|
||||
return 1; /* error */
|
||||
} else {
|
||||
mmc_log_debug(&log, "unexpected HW interrupt 0x%08x mask 0X%08x\n", v, mask);
|
||||
if (sys_irqenable(&hook_id) != OK)
|
||||
printf
|
||||
("Failed to re-enable irqenable irq\n");
|
||||
continue;
|
||||
// return 1;
|
||||
}
|
||||
default:
|
||||
/*
|
||||
* unhandled message. queue it and
|
||||
* handle it in the blockdriver loop.
|
||||
*/
|
||||
blockdriver_mq_queue(&m, ipc_status);
|
||||
}
|
||||
} else {
|
||||
mmc_log_debug(&log, "Other\n");
|
||||
/*
|
||||
* unhandled message. queue it and handle it in the
|
||||
* blockdriver loop.
|
||||
*/
|
||||
blockdriver_mq_queue(&m, ipc_status);
|
||||
}
|
||||
}
|
||||
sys_setalarm(0, 0); /* cancel the alarm */
|
||||
|
||||
#else
|
||||
spin_t spin;
|
||||
spin_init(&spin, SANE_TIMEOUT);
|
||||
/* Wait for completion */
|
||||
int counter =0;
|
||||
while (1 == 1) {
|
||||
counter ++;
|
||||
v = read32(base_address + MMCHS_SD_STAT);
|
||||
if (spin_check(&spin) == FALSE) {
|
||||
mmc_log_warn(&log, "Timeout waiting for interrupt (%d) value 0x%08x mask 0x%08x\n",counter, v,mask);
|
||||
return 1;
|
||||
}
|
||||
if (v & mask) {
|
||||
return 0;
|
||||
} else if (v & 0xFF00) {
|
||||
mmc_log_debug(&log, "unexpected HW interrupt (%d) 0x%08x mask 0x%08x\n", v, mask);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 1; /* unreached */
|
||||
#endif /* USE_INTR */
|
||||
}
|
||||
|
||||
void
|
||||
intr_assert(int mask)
|
||||
{
|
||||
if (read32(base_address + MMCHS_SD_STAT) & 0x8000) {
|
||||
mmc_log_debug(&log, "%s, error stat %08x\n", __FUNCTION__,
|
||||
read32(base_address + MMCHS_SD_STAT));
|
||||
set32(base_address + MMCHS_SD_STAT, MMCHS_SD_STAT_ERROR_MASK,
|
||||
0xffffffffu);
|
||||
} else {
|
||||
write32(base_address + MMCHS_SD_STAT, mask);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
mmchs_send_cmd(uint32_t command, uint32_t arg)
|
||||
{
|
||||
int count = 0;
|
||||
|
||||
/* Read current interrupt status and fail it an interrupt is already
|
||||
* asserted */
|
||||
if ((read32(base_address + MMCHS_SD_STAT) & 0xffffu)) {
|
||||
mmc_log_warn(&log, "%s, interrupt already raised stat %08x\n",
|
||||
__FUNCTION__, read32(base_address + MMCHS_SD_STAT));
|
||||
write32(base_address + MMCHS_SD_STAT,
|
||||
MMCHS_SD_IE_CC_ENABLE_CLEAR);
|
||||
// return 1;
|
||||
}
|
||||
|
||||
/* Set arguments */
|
||||
write32(base_address + MMCHS_SD_ARG, arg);
|
||||
/* Set command */
|
||||
set32(base_address + MMCHS_SD_CMD, MMCHS_SD_CMD_MASK, command);
|
||||
|
||||
/* Wait for completion */
|
||||
while ((read32(base_address + MMCHS_SD_STAT) & 0xffffu) == 0x0) {
|
||||
count++;
|
||||
}
|
||||
|
||||
if (read32(base_address + MMCHS_SD_STAT) & 0x8000) {
|
||||
mmc_log_warn(&log, "%s, error stat %08x\n", __FUNCTION__,
|
||||
read32(base_address + MMCHS_SD_STAT));
|
||||
set32(base_address + MMCHS_SD_STAT, MMCHS_SD_STAT_ERROR_MASK,
|
||||
0xffffffffu);
|
||||
if (intr_wait(MMCHS_SD_STAT_CC | MMCHS_SD_IE_TC_ENABLE_CLEAR)) {
|
||||
intr_assert(MMCHS_SD_STAT_CC);
|
||||
mmc_log_warn(&log, "Failure waiting for interrupt\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -281,16 +417,20 @@ mmchs_send_cmd(uint32_t command, uint32_t arg)
|
|||
/*
|
||||
* Command with busy response *CAN* also set the TC bit if they exit busy
|
||||
*/
|
||||
while ((read32(base_address + MMCHS_SD_STAT)
|
||||
if ((read32(base_address + MMCHS_SD_STAT)
|
||||
& MMCHS_SD_IE_TC_ENABLE_ENABLE) == 0) {
|
||||
count++;
|
||||
mmc_log_warn(&log, "TC should be raised\n");
|
||||
}
|
||||
write32(base_address + MMCHS_SD_STAT,
|
||||
MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
}
|
||||
|
||||
/* clear the cc status */
|
||||
write32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_CC_ENABLE_CLEAR);
|
||||
if (intr_wait(MMCHS_SD_STAT_CC | MMCHS_SD_IE_TC_ENABLE_CLEAR)) {
|
||||
intr_assert(MMCHS_SD_STAT_CC);
|
||||
mmc_log_warn(&log, "Failure waiting for clear\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
intr_assert(MMCHS_SD_STAT_CC);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -383,10 +523,11 @@ card_identification()
|
|||
int
|
||||
card_query_voltage_and_type(struct sd_card_regs *card)
|
||||
{
|
||||
|
||||
spin_t spin;
|
||||
command.cmd = MMC_APP_CMD;
|
||||
command.resp_type = RESP_LEN_48;
|
||||
command.args = MMC_ARG_RCA(0x0); /* RCA=0000 */
|
||||
|
||||
if (mmc_send_cmd(&command)) {
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -405,6 +546,7 @@ card_query_voltage_and_type(struct sd_card_regs *card)
|
|||
return 1;
|
||||
}
|
||||
/* @todo wait for max 1 ms */
|
||||
spin_init(&spin, SANE_TIMEOUT);
|
||||
while (!(command.resp[0] & MMC_OCR_MEM_READY)) {
|
||||
command.cmd = MMC_APP_CMD;
|
||||
command.resp_type = RESP_LEN_48;
|
||||
|
|
@ -432,6 +574,10 @@ card_query_voltage_and_type(struct sd_card_regs *card)
|
|||
if ((command.resp[0] & MMC_OCR_MEM_READY)) {
|
||||
break;
|
||||
}
|
||||
if (spin_check(&spin) == FALSE) {
|
||||
mmc_log_warn(&log,
|
||||
"TIMEOUT waiting for the SD card\n");
|
||||
}
|
||||
|
||||
}
|
||||
card->ocr = command.resp[3];
|
||||
|
|
@ -536,15 +682,18 @@ read_single_block(struct sd_card_regs *card,
|
|||
| MMCHS_SD_CMD_MSBS_SINGLE /* single block */
|
||||
| MMCHS_SD_CMD_DDIR_READ /* read data from card */
|
||||
, blknr)) {
|
||||
mmc_log_warn(&log, "Error sending command\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
while ((read32(base_address + MMCHS_SD_STAT)
|
||||
& MMCHS_SD_IE_BRR_ENABLE_ENABLE) == 0) {
|
||||
count++;
|
||||
if (intr_wait(MMCHS_SD_IE_BRR_ENABLE_ENABLE)) {
|
||||
intr_assert(MMCHS_SD_IE_BRR_ENABLE_ENABLE);
|
||||
mmc_log_warn(&log, "Timeout waiting for interrupt\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (!(read32(base_address + MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BRE_EN)) {
|
||||
mmc_log_warn(&log, "Problem BRE should be true\n");
|
||||
return 1; /* We are not allowed to read data from the
|
||||
* data buffer */
|
||||
}
|
||||
|
|
@ -558,11 +707,12 @@ read_single_block(struct sd_card_regs *card,
|
|||
}
|
||||
|
||||
/* Wait for TC */
|
||||
while ((read32(base_address +
|
||||
MMCHS_SD_STAT) & MMCHS_SD_IE_TC_ENABLE_ENABLE)
|
||||
== 0) {
|
||||
count++;
|
||||
if (intr_wait(MMCHS_SD_IE_TC_ENABLE_ENABLE)) {
|
||||
intr_assert(MMCHS_SD_IE_TC_ENABLE_ENABLE);
|
||||
mmc_log_warn(&log, "Timeout waiting for interrupt\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
write32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
|
||||
/* clear and disable the bbr interrupt */
|
||||
|
|
@ -579,17 +729,21 @@ write_single_block(struct sd_card_regs *card,
|
|||
uint32_t count;
|
||||
uint32_t value;
|
||||
|
||||
count = 0;
|
||||
if ((read32(base_address + MMCHS_SD_STAT) & 0xffffu)) {
|
||||
mmc_log_warn(&log, "%s, interrupt already raised stat %08x\n",
|
||||
__FUNCTION__, read32(base_address + MMCHS_SD_STAT));
|
||||
write32(base_address + MMCHS_SD_STAT,
|
||||
MMCHS_SD_IE_CC_ENABLE_CLEAR);
|
||||
// return 1;
|
||||
}
|
||||
|
||||
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_BWR_ENABLE,
|
||||
MMCHS_SD_IE_BWR_ENABLE_ENABLE);
|
||||
count = 0;
|
||||
|
||||
// set32(base_address + MMCHS_SD_IE, 0xfff , 0xfff);
|
||||
set32(base_address + MMCHS_SD_BLK, MMCHS_SD_BLK_BLEN, 512);
|
||||
|
||||
/* Set timeout */
|
||||
set32(base_address + MMCHS_SD_SYSCTL, MMCHS_SD_SYSCTL_DTO,
|
||||
MMCHS_SD_SYSCTL_DTO_2POW27);
|
||||
|
||||
/* write single block */
|
||||
if (mmchs_send_cmd(MMCHS_SD_CMD_INDX_CMD(MMC_WRITE_BLOCK_SINGLE)
|
||||
| MMCHS_SD_CMD_DP_DATA /* Command with data transfer */
|
||||
|
|
@ -597,19 +751,32 @@ write_single_block(struct sd_card_regs *card,
|
|||
| MMCHS_SD_CMD_MSBS_SINGLE /* single block */
|
||||
| MMCHS_SD_CMD_DDIR_WRITE /* write to the card */
|
||||
, blknr)) {
|
||||
mmc_log_warn(&log, "Write single block command failed\n");
|
||||
mmc_log_trace(&log, "STAT=(0x%08x)\n",
|
||||
read32(base_address + MMCHS_SD_STAT));
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Wait for the MMCHS_SD_IE_BWR_ENABLE interrupt */
|
||||
while ((read32(base_address +
|
||||
MMCHS_SD_STAT) & MMCHS_SD_IE_BWR_ENABLE) == 0) {
|
||||
count++;
|
||||
if (intr_wait(MMCHS_SD_IE_BWR_ENABLE)) {
|
||||
intr_assert(MMCHS_SD_IE_BWR_ENABLE);
|
||||
mmc_log_warn(&log, "WFI failed\n");
|
||||
return 1;
|
||||
}
|
||||
/* clear the interrupt directly */
|
||||
intr_assert(MMCHS_SD_IE_BWR_ENABLE);
|
||||
|
||||
if (!(read32(base_address + MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BWE_EN)) {
|
||||
mmc_log_warn(&log,
|
||||
"Error expected Buffer to be write enabled\n");
|
||||
return 1; /* not ready to write data */
|
||||
}
|
||||
|
||||
|
||||
for (count = 0; count < 512; count += 4) {
|
||||
while (!(read32(base_address + MMCHS_SD_PSTATE) & MMCHS_SD_PSTATE_BWE_EN)){
|
||||
mmc_log_trace(&log, "Error expected Buffer to be write enabled(%d)\n", count);
|
||||
}
|
||||
*((char *) &value) = buf[count];
|
||||
*((char *) &value + 1) = buf[count + 1];
|
||||
*((char *) &value + 2) = buf[count + 2];
|
||||
|
|
@ -617,17 +784,14 @@ write_single_block(struct sd_card_regs *card,
|
|||
write32(base_address + MMCHS_SD_DATA, value);
|
||||
}
|
||||
|
||||
|
||||
/* Wait for TC */
|
||||
while ((read32(base_address +
|
||||
MMCHS_SD_STAT) & MMCHS_SD_IE_TC_ENABLE_ENABLE)
|
||||
== 0) {
|
||||
count++;
|
||||
if (intr_wait(MMCHS_SD_IE_TC_ENABLE_CLEAR)) {
|
||||
intr_assert(MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
mmc_log_warn(&log, "(Write) Timeout waiting for transfer complete\n");
|
||||
return 1;
|
||||
}
|
||||
write32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
write32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_CC_ENABLE_CLEAR); /* finished.
|
||||
*/
|
||||
/* clear the bwr interrupt FIXME is this right when writing? */
|
||||
write32(base_address + MMCHS_SD_STAT, MMCHS_SD_IE_BWR_ENABLE_CLEAR);
|
||||
intr_assert(MMCHS_SD_IE_TC_ENABLE_CLEAR);
|
||||
set32(base_address + MMCHS_SD_IE, MMCHS_SD_IE_BWR_ENABLE,
|
||||
MMCHS_SD_IE_BWR_ENABLE_DISABLE);
|
||||
return 0;
|
||||
|
|
@ -661,7 +825,7 @@ mmchs_host_set_instance(struct mmc_host *host, int instance)
|
|||
int
|
||||
mmchs_host_reset(struct mmc_host *host)
|
||||
{
|
||||
mmchs_init(1);
|
||||
// mmchs_init(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -675,7 +839,7 @@ mmchs_card_detect(struct sd_slot *slot)
|
|||
struct sd_card *
|
||||
mmchs_card_initialize(struct sd_slot *slot)
|
||||
{
|
||||
mmchs_init(1);
|
||||
// mmchs_init(1);
|
||||
|
||||
struct sd_card *card;
|
||||
card = &slot->card;
|
||||
|
|
@ -785,6 +949,7 @@ host_initialize_host_structure_mmchs(struct mmc_host *host)
|
|||
host->card_detect = mmchs_card_detect;
|
||||
host->card_initialize = mmchs_card_initialize;
|
||||
host->card_release = mmchs_card_release;
|
||||
host->hw_intr = mmchs_hw_intr;
|
||||
host->read = mmchs_host_read;
|
||||
host->write = mmchs_host_write;
|
||||
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#define MMCHS_SD_SYSCTL 0x22c /* SD System control (reset,clocks and timeout) */
|
||||
#define MMCHS_SD_STAT 0x230 /* SD Interrupt status */
|
||||
#define MMCHS_SD_IE 0x234 /* SD Interrupt Enable register */
|
||||
#define MMCHS_SD_ISE 0x238 /* SD Interrupt Signal Enable register */
|
||||
#define MMCHS_SD_CAPA 0x240 /* Capabilities of the host controller */
|
||||
#define MMCHS_SD_CUR_CAPA 0x248 /* Current capabilities of the host controller */
|
||||
|
||||
|
|
@ -146,7 +147,7 @@
|
|||
#define MMCHS_SD_SYSCTL_DTO (0xf << 16) /* Data timeout counter */
|
||||
#define MMCHS_SD_SYSCTL_DTO_2POW13 (0x0 << 16) /* TCF x 2^13 */
|
||||
#define MMCHS_SD_SYSCTL_DTO_2POW14 (0x1 << 16) /* TCF x 2^14 */
|
||||
#define MMCHS_SD_SYSCTL_DTO_2POW27 (0x3 << 16) /* TCF x 2^27 */
|
||||
#define MMCHS_SD_SYSCTL_DTO_2POW27 (0xe << 16) /* TCF x 2^27 */
|
||||
|
||||
#define MMCHS_SD_STAT_ERRI (0x01 << 15) /* Error interrupt */
|
||||
#define MMCHS_SD_STAT_ERROR_MASK (0xff << 15 | 0x3 << 24 | 0x03 << 28)
|
||||
|
|
|
|||
|
|
@ -549,6 +549,9 @@ service mmc
|
|||
{
|
||||
system
|
||||
PRIVCTL # 4
|
||||
IRQCTL # 19
|
||||
;
|
||||
irq 83; # IRQ 83 allowed
|
||||
;
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue