Lan8710 driver initial version, after first review
Change-Id: If00cf1e098da5875eb040f8765273a6fa5e43e33
This commit is contained in:
Michal Maka
Ben Gras
parent
2343037ba2
commit
29ecfde5ef
8 changed files with 1652 additions and 1 deletions
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@ -4,6 +4,7 @@
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./boot/minix/.temp/mod10_vm minix-sys
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./boot/minix/.temp/mod11_pfs minix-sys
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./boot/minix/.temp/mod12_init minix-sys
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./etc/system.conf.d/lan8710a minix-sys
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./multiboot/mod07_log minix-sys
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./multiboot/mod08_tty minix-sys
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./multiboot/mod09_mfs minix-sys
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@ -108,6 +109,7 @@
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./usr/sbin/fb minix-sys
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./usr/sbin/gpio minix-sys
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./usr/sbin/i2c minix-sys
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./usr/sbin/lan8710a minix-sys
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./usr/sbin/random minix-sys
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./usr/sbin/tda19988 minix-sys
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./usr/tests/minix-posix/mod minix-sys
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@ -23,7 +23,7 @@ SUBDIR= ahci amddev atl2 at_wini audio dec21140A dp8390 dpeth \
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.endif
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.if ${MACHINE_ARCH} == "earm"
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SUBDIR= cat24c256 fb gpio i2c mmc log tda19988 tty random
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SUBDIR= cat24c256 fb gpio i2c mmc log tda19988 tty random lan8710a
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.endif
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.endif # ${MKIMAGEONLY} != "yes"
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16
drivers/lan8710a/Makefile
Normal file
16
drivers/lan8710a/Makefile
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@ -0,0 +1,16 @@
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# Makefile for the lan8710a ethernet driver.
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PROG= lan8710a
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SRCS= lan8710a.c
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FILES=$(PROG).conf
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FILESNAME=$(PROG)
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FILESDIR= /etc/system.conf.d
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DPADD+= ${LIBNETDRIVER} ${LIBSYS} ${LIBTIMERS}
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LDADD+= -lnetdriver -lsys -ltimers
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MAN=
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BINDIR?= /usr/sbin
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.include <minix.service.mk>
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41
drivers/lan8710a/README.txt
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41
drivers/lan8710a/README.txt
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@ -0,0 +1,41 @@
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--------------------------------------------------------------------------------
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* INFORMATION: *
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--------------------------------------------------------------------------------
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README file for the LAN8710A ethernet board driver for BeagleBone Rev. A6a
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created July 2013, JPEmbedded (info@jpembedded.eu)
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--------------------------------------------------------------------------------
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* INSTALLATION: *
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--------------------------------------------------------------------------------
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To install LAN8710A for BeagleBone under MINIX you have to edit /etc/inet.conf
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by adding line:
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eth0 lan8710a 0 { default; };
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and changing:
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psip0 { default; };
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to:
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psip1;
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Restart the system and the driver should work.
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--------------------------------------------------------------------------------
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* TESTS: *
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--------------------------------------------------------------------------------
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Driver was tested using various tools, i. e.
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* fetch - downloading file from the Internet and also local server. Every file
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downloaded well, but speed was about 50-200 kB/s.
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* ftp - downloading and uploading 20 MB file completed.
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* ping - checking connection between BeagleBone and computer passed using stan -
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dard settings, when we set ping requests interval to 200 ms it also
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passed. But with 20 ms and 2 ms driver dropped some packets (20 ms -
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about 20% loss, 2 ms - 50% loss).
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* udpstat, hostaddr, dhcpd, ifconfig, arp gave proper results.
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Tests passed, so driver meets the requirements of ethernet driver.
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--------------------------------------------------------------------------------
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* LIMITATION: *
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--------------------------------------------------------------------------------
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Download speed: 50-200 kB/s
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Low bandwidth is probably caused by memory copy functions. Standard Linux driver
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copies packets data directly to destination buffer using DMA. Minix driver needs
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to do a safe copy (sys_safecopyfrom and sys_safecopyto) from local buffer to the
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system buffer. This operation slows down the whole driver.
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1249
drivers/lan8710a/lan8710a.c
Normal file
1249
drivers/lan8710a/lan8710a.c
Normal file
File diff suppressed because it is too large
Load diff
17
drivers/lan8710a/lan8710a.conf
Normal file
17
drivers/lan8710a/lan8710a.conf
Normal file
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@ -0,0 +1,17 @@
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service lan8710a
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{
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type net;
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descr "Beaglebone Ethernet Controller LAN8710A";
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system
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PRIVCTL # 4
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UMAP # 14
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IRQCTL # 19
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DEVIO # 21
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;
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ipc
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tty inet lwip
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;
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irq 41 # IRQ 41 allowed
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42 # IRQ 42 allowed
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;
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};
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123
drivers/lan8710a/lan8710a.h
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123
drivers/lan8710a/lan8710a.h
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@ -0,0 +1,123 @@
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#ifndef LAN8710A_H_
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#define LAN8710A_H_
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#include <net/gen/ether.h>
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#define LAN8710A_DEBUG (1)
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#if LAN8710A_DEBUG == 1
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#define LAN8710A_DEBUG_PRINT(args) \
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do { \
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printf("LAN8710A DEBUG: "); \
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printf args; \
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printf("\n"); \
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} while (0)
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#else
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#define LAN8710A_DEBUG_PRINT(args)
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#endif
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#ifndef ERR
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#define ERR (-1) /* general error flag */
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#endif
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#ifndef OK
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#define OK 0 /* general OK flag */
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#endif
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#define MAP_FAILED ((void *) -1) /* mmap() failed */
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/* Ethernet driver defines */
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#define LAN8710A_NAME_LEN (11)
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/* Ethernet driver states */
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#define LAN8710A_DETECTED (1 << 0)
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#define LAN8710A_ENABLED (1 << 1)
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#define LAN8710A_READING (1 << 2)
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#define LAN8710A_WRITING (1 << 3)
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#define LAN8710A_RECEIVED (1 << 4)
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#define LAN8710A_TRANSMIT (1 << 5)
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/* Descriptors flags */
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#define LAN8710A_DESC_FLAG_OWN (1 << 29) /* ownership flag */
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#define LAN8710A_DESC_FLAG_SOP (1 << 31) /* start of packet flag */
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#define LAN8710A_DESC_FLAG_EOP (1 << 30) /* end of packet flag */
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/* Number of Tx and Rx interrupts */
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#define LAN8710A_RX_INTR (41)
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#define LAN8710A_TX_INTR (42)
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/* Values to be written after interrupt handle and interrupt masks*/
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#define RX_INT (1)
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#define TX_INT (2)
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/** Numbers of Tx DMA channels */
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#define TX_DMA_CHANNELS (8)
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/** Number of transmit descriptors */
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#define LAN8710A_NUM_TX_DESC (255)
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/** Number of receive descriptors */
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#define LAN8710A_NUM_RX_DESC (255)
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/** Number of I/O vectors to use. */
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#define LAN8710A_IOVEC_NR (16)
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/** Size of each I/O buffer per descriptor. */
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#define LAN8710A_IOBUF_SIZE (1520)
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/** MAC address override variable. */
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#define LAN8710A_ENVVAR "LAN8710AETH"
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/** MAX DMA Channels */
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#define DMA_MAX_CHANNELS (8)
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/* Setting of Tx descriptors */
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#define TX_DESC_TO_PORT1 (1 << 16)
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#define TX_DESC_TO_PORT_EN (1 << 20)
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typedef struct lan8710a_desc_t
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{
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u32_t next_pointer;
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u32_t buffer_pointer;
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u32_t buffer_length_off;
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u32_t pkt_len_flags;
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} lan8710a_desc_t;
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typedef struct lan8710a_t
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{
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lan8710a_desc_t *rx_desc;
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lan8710a_desc_t *tx_desc;
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phys_bytes rx_desc_phy;
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phys_bytes tx_desc_phy;
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char name[LAN8710A_NAME_LEN];
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int status;
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int irq_rx_hook; /* Rx interrupt Request Vector Hook. */
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int irq_tx_hook; /* Tx interrupt Request Vector Hook. */
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int instance;
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ether_addr_t address; /* Ethernet MAC address. */
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u8_t *regs;
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u32_t phy_address;
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u8_t *p_rx_buf; /* pointer to the buffer with receive frames */
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u8_t *p_tx_buf; /* pointer to the buffer with transmit frames */
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u16_t tx_desc_idx; /* index of the next transmit desciptor */
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u16_t rx_desc_idx; /* index of the next receive desciptor */
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int client;
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message tx_message;
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message rx_message;
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unsigned int rx_size;
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/* register mapping */
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vir_bytes regs_cp_per;
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vir_bytes regs_mdio;
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vir_bytes regs_cpsw_cpdma;
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vir_bytes regs_ctrl_mod;
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vir_bytes regs_cpsw_sl;
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vir_bytes regs_cpsw_ss;
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vir_bytes regs_cpsw_stats;
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vir_bytes regs_cpsw_ale;
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vir_bytes regs_cpsw_wr;
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vir_bytes regs_intc;
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vir_bytes regs_cpdma_stram;
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} lan8710a_t;
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#endif /* LAN8710A_H_ */
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203
drivers/lan8710a/lan8710a_reg.h
Normal file
203
drivers/lan8710a/lan8710a_reg.h
Normal file
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@ -0,0 +1,203 @@
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#ifndef LAN8710A_REG_H_
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#define LAN8710A_REG_H_
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/* How much memory we should map */
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#define MEMORY_LIMIT (0x5302000)
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#define BEGINNING_DESC_MEM (0x4A102000)
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#define DESC_MEMORY_LIMIT (0x2000)
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#define BEGINNING_RX_DESC_MEM (0x4A102000)
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#define BEGINNING_TX_DESC_MEM (0x4A103000)
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/* MDIO Registers */
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#define MDIO_BASE_ADDR (0x4A101000)
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#define MDIOVER ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x00))
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#define MDIOCONTROL ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x04))
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#define MDIOALIVE ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x08))
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#define MDIOLINK ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x0C))
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#define MDIOLINKINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x10))
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#define MDIOLINKINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x14))
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#define MDIOUSERINTRAW ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x20))
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#define MDIOUSERINTMASKED ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x24))
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#define MDIOUSERINTMASKSET ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x28))
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#define MDIOUSERINTMASKCLR ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x2C))
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#define MDIOUSERACCESS0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x80))
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#define MDIOUSERPHYSEL0 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x84))
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#define MDIOUSERACCESS1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x88))
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#define MDIOUSERPHYSEL1 ((volatile u32_t *)( lan8710a_state.regs_mdio + 0x8C))
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#define MDIO_PREAMBLE (1 << 20)
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#define MDCLK_DIVIDER (0x255)
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#define MDIO_ENABLE (1 << 30)
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#define MDIO_GO (1 << 31)
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#define MDIO_WRITE (1 << 30)
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#define MDIO_ACK (1 << 29)
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#define MDIO_REGADR (21)
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#define MDIO_PHYADR (16)
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#define MDIO_DATA (0)
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/* CONTROL MODULE Registers */
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#define CTRL_MOD_BASE_ADR (0x44E10000)
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#define CTRL_MAC_ID0_LO ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x630))
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#define CTRL_MAC_ID0_HI ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x634))
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#define GMII_SEL ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x650))
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#define CONF_MII1_COL ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x908))
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#define CONF_MII1_CRS ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x90C))
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#define CONF_MII1_RX_ER ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x910))
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#define CONF_MII1_TX_EN ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x914))
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#define CONF_MII1_RX_DV ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x918))
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#define CONF_MII1_TXD3 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x91C))
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#define CONF_MII1_TXD2 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x920))
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#define CONF_MII1_TXD1 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x924))
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#define CONF_MII1_TXD0 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x928))
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#define CONF_MII1_TX_CLK ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x92C))
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#define CONF_MII1_RX_CLK ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x930))
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#define CONF_MII1_RXD3 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x934))
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#define CONF_MII1_RXD2 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x938))
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#define CONF_MII1_RXD1 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x93C))
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#define CONF_MII1_RXD0 ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x940))
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#define CONF_MDIO ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x948))
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#define CONF_MDC ((volatile u32_t *)( lan8710a_state.regs_ctrl_mod + 0x94C))
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#define CONF_MOD_SLEW_CTRL (1 << 6)
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#define CONF_MOD_RX_ACTIVE (1 << 5)
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#define CONF_MOD_PU_TYPESEL (1 << 4)
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#define CONF_MOD_PUDEN (1 << 3)
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#define CONF_MOD_MMODE_MII (7 << 0)
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#define RMII1_IO_CLK_EN (1 << 6)
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#define RGMII1_IDMODE (1 << 4)
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#define GMII2_SEL_BIT1 (1 << 3)
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#define GMII2_SEL_BIT0 (1 << 2)
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#define GMII1_SEL_BIT1 (1 << 1)
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#define GMII1_SEL_BIT0 (1 << 0)
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/* CLOCK MODULE Registers */
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#define CM_PER_BASE_ADR (0x44E00000)
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#define CM_PER_CPSW_CLKSTCTRL ((volatile u32_t *)( lan8710a_state.regs_cp_per + 0x144))
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#define CM_PER_CPSW_CLKSTCTRL_BIT1 (1 << 1)
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#define CM_PER_CPSW_CLKSTCTRL_BIT0 (1 << 0)
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/* CPSW_ALE Registers */
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#define CPSW_ALE_BASE_ADR (0x4A100D00)
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#define CPSW_ALE_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x08))
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#define CPSW_ALE_PORTCTL0 ((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x40))
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#define CPSW_ALE_PORTCTL1 ((volatile u32_t *)( lan8710a_state.regs_cpsw_ale + 0x44))
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#define CPSW_ALE_ENABLE (1 << 31)
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#define CPSW_ALE_BYPASS (1 << 4)
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#define CPSW_ALE_PORT_FWD (3 << 0)
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/* CPSW_SL Registers */
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#define CPSW_SL_BASE_ADR (0x4A100D80)
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#define CPSW_SL_MACCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x04))
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#define CPSW_SL_SOFT_RESET(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x0C))
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#define CPSW_SL_RX_MAXLEN(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x10))
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#define CPSW_SL_BOFFTEST(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x14))
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#define CPSW_SL_EMCONTROL(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x20))
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#define CPSW_SL_RX_PRI_MAP(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x24))
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#define CPSW_SL_TX_GAP(x) ((volatile u32_t *)( lan8710a_state.regs_cpsw_sl + ((x)-1)*64 + 0x28))
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#define CPSW_SL_GMII_EN (1 << 5)
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#define CPSW_SL_FULLDUPLEX (1 << 0)
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#define SOFT_RESET (1 << 0)
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/* CPSW_STATS Registers */
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#define CPSW_STATS_BASE_ADR (0x4A100900)
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#define CPSW_STATS_MEM_LIMIT (0x90)
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#define CPSW_STAT_RX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x00))
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#define CPSW_STAT_RX_CRC_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x10))
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#define CPSW_STAT_RX_AGNCD_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x14))
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#define CPSW_STAT_RX_OVERSIZE ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x18))
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#define CPSW_STAT_TX_GOOD ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x34))
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#define CPSW_STAT_COLLISIONS ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x48))
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#define CPSW_STAT_TX_UNDERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x5C))
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#define CPSW_STAT_CARR_SENS_ERR ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x60))
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#define CPSW_STAT_RX_OVERRUN ((volatile u32_t *)( lan8710a_state.regs_cpsw_stats + 0x8C))
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/* CPSW_CPDMA Registers */
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#define CPSW_CPDMA_BASE_ADR (0x4A100800)
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||||
#define CPDMA_SOFT_RESET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x1C))
|
||||
#define CPDMA_TX_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x04))
|
||||
#define CPDMA_RX_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x14))
|
||||
#define CPDMA_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x20))
|
||||
#define CPDMA_STATUS ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x24))
|
||||
#define CPDMA_RX_BUFFER_OFFSET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x28))
|
||||
#define CPDMA_EMCONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x2C))
|
||||
#define CPDMA_TX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x88))
|
||||
#define CPDMA_TX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x8C))
|
||||
#define CPDMA_EOI_VECTOR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0x94))
|
||||
#define CPDMA_RX_INTMASK_SET ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xA8))
|
||||
#define CPDMA_RX_INTMASK_CLEAR ((volatile u32_t *)( lan8710a_state.regs_cpsw_cpdma + 0xAC))
|
||||
|
||||
#define CPDMA_IDLE (1 << 31)
|
||||
#define CPDMA_TX_RLIM (0xFF << 8)
|
||||
#define CPDMA_NO_OFFSET (0xFFFF << 0)
|
||||
#define CPDMA_RX_CEF (1 << 4)
|
||||
#define CPDMA_CMD_IDLE (1 << 3)
|
||||
#define RX_OFFLEN_BLOCK (1 << 2)
|
||||
#define RX_OWNERSHIP (1 << 1)
|
||||
#define TX_PTYPE (1 << 0)
|
||||
#define CPDMA_TX_EN (1 << 0)
|
||||
#define CPDMA_RX_EN (1 << 0)
|
||||
#define CPDMA_FIRST_CHAN_INT (1 << 0)
|
||||
#define CPDMA_ALL_CHAN_INT (0xFF << 0)
|
||||
#define CPDMA_TX_PTYPE (1 << 0)
|
||||
#define CPDMA_ERROR (0x00F7F700)
|
||||
|
||||
/* CPSW_SS Registers */
|
||||
#define CPSW_SS_BASE_ADR (0x4A100000)
|
||||
#define CPSW_SS_SOFT_RESET ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x08))
|
||||
#define CPSW_SS_STAT_PORT_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x0C))
|
||||
#define CPSW_SS_TX_START_WDS ((volatile u32_t *)( lan8710a_state.regs_cpsw_ss + 0x20))
|
||||
|
||||
#define CPSW_P2_STAT_EN (1 << 2)
|
||||
#define CPSW_P1_STAT_EN (1 << 1)
|
||||
#define CPSW_P0_STAT_EN (1 << 0)
|
||||
|
||||
/* CPSW_WR Registers */
|
||||
#define CPSW_WR_BASE_ADR (0x4A101200)
|
||||
#define CPSW_WR_INT_CONTROL ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x0C))
|
||||
#define CPSW_WR_C0_RX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x14))
|
||||
#define CPSW_WR_C1_RX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x24))
|
||||
#define CPSW_WR_C2_RX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x34))
|
||||
#define CPSW_WR_C0_RX_STAT ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x44))
|
||||
#define CPSW_WR_C0_TX_EN ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x18))
|
||||
#define CPSW_WR_C0_TX_STAT ((volatile u32_t *)( lan8710a_state.regs_cpsw_wr + 0x48))
|
||||
|
||||
#define CPSW_FIRST_CHAN_INT (1 << 0)
|
||||
#define CPSW_ALL_CHAN_INT (0xFF << 0)
|
||||
|
||||
/* INTERRUPTION CONTROLLER Registers */
|
||||
#define INTC_BASE_ADR (0x48200000)
|
||||
#define INTC_SYSCONFIG ((volatile u32_t *)( lan8710a_state.regs_intc + 0x10))
|
||||
#define INTC_IDLE ((volatile u32_t *)( lan8710a_state.regs_intc + 0x50))
|
||||
#define INTC_MIR_CLEAR1 ((volatile u32_t *)( lan8710a_state.regs_intc + 0xA8))
|
||||
#define INTC_ILR(x) ((volatile u32_t *)( lan8710a_state.regs_intc + 0x100 + 4*(x)))
|
||||
|
||||
#define INTC_AUTOIDLE (1 << 0)
|
||||
#define INTC_FUNCIDLE (1 << 0)
|
||||
#define INTC_TURBO (1 << 1)
|
||||
#define INTC_FIQnIRQ (1 << 0)
|
||||
#define INTC_RX_MASK (1 << 9)
|
||||
#define INTC_TX_MASK (1 << 10)
|
||||
|
||||
/* DMA STATERAM Registers */
|
||||
#define CPDMA_STRAM_BASE_ADR (0x4A100A00)
|
||||
#define CPDMA_STRAM_TX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 4*(x)))
|
||||
#define CPDMA_STRAM_RX_HDP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x20 + 4*(x)))
|
||||
#define CPDMA_STRAM_TX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x40 + 4*(x)))
|
||||
#define CPDMA_STRAM_RX_CP(x) ((volatile u32_t *)( lan8710a_state.regs_cpdma_stram + 0x60 + 4*(x)))
|
||||
|
||||
#define ALL_BITS (0xFFFFFFFF)
|
||||
|
||||
/* LAN8710A Registers */
|
||||
#define PHY_REGISTERS (31)
|
||||
#define LAN8710A_CTRL_REG (0)
|
||||
#define LAN8710A_STATUS_REG (1)
|
||||
|
||||
#define LAN8710A_SOFT_RESET (1 << 15)
|
||||
#define LAN8710A_AUTO_NEG (1 << 12)
|
||||
#define LAN8710A_AUTO_NEG_COMPL (1 << 5)
|
||||
|
||||
#endif /* LAN8710A_REG_H_ */
|
||||
Loading…
Reference in a new issue