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Intel Pro/1000 driver written by Niek Linnenbank.

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This commit is contained in:
Ben Gras 2009-12-07 18:33:41 +00:00
parent f0db9bb328
commit 26ba254a4a
10 changed files with 2144 additions and 9 deletions
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22
commands/scripts/netconf.sh
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@ -103,10 +103,14 @@ cards()
"1186:1340" "11DB:1234" "1259:A117" "1259:A11E" "126C:1211" \ "1186:1340" "11DB:1234" "1259:A117" "1259:A11E" "126C:1211" \
"13D1:AB06" "1432:9130" "14EA:AB06" "14EA:AB07" "1500:1360" \ "13D1:AB06" "1432:9130" "14EA:AB06" "14EA:AB07" "1500:1360" \
"1743:8139" "4033:1360" "1743:8139" "4033:1360"
card 4 "Realtek 8029 based card (also emulated by Qemu)" "10EC:8029" card 4 "Realtek 8169 based card" \
card 5 "NE2000, 3com 503 or WD based card (also emulated by Bochs)" "10EC:8129" "10EC:8167" "10EC:8169" "1186:4300" "1259:C107" \
card 6 "AMD LANCE (also emulated by VMWare and VirtualBox)" "1022:2000" "1385:8169" "16EC:0116" "1737:1032"
card 7 "Different Ethernet card (no networking)" card 5 "Realtek 8029 based card (also emulated by Qemu)" "10EC:8029"
card 6 "NE2000, 3com 503 or WD based card (also emulated by Bochs)"
card 7 "AMD LANCE (also emulated by VMWare and VirtualBox)" "1022:2000"
card 8 "Intel PRO/1000 Gigabit" "8086:100E" "8086:107C" "8086:10CD"
card 9 "Different Ethernet card (no networking)"
} }
warn() warn()
@ -143,15 +147,17 @@ drv_params()
test "$v" = 1 && echo "" test "$v" = 1 && echo ""
test "$v" = 1 && echo "Note: After installing, edit $LOCALRC to the right configuration." test "$v" = 1 && echo "Note: After installing, edit $LOCALRC to the right configuration."
;; ;;
4) driver=rtl8169; ;;
3) driver=rtl8139; ;; 3) driver=rtl8139; ;;
4) driver=dp8390; driverargs="dp8390_arg='DPETH0=pci'"; ;; 5) driver=dp8390; driverargs="dp8390_arg='DPETH0=pci'"; ;;
5) driver=dp8390; driverargs="dp8390_arg='DPETH0=240:9'"; 6) driver=dp8390; driverargs="dp8390_arg='DPETH0=240:9'";
test "$v" = 1 && echo "" test "$v" = 1 && echo ""
test "$v" = 1 && echo "Note: After installing, edit $LOCALRC to the right configuration." test "$v" = 1 && echo "Note: After installing, edit $LOCALRC to the right configuration."
test "$v" = 1 && echo " chose option 4, the defaults for emulation by Bochs have been set." test "$v" = 1 && echo " chose option 4, the defaults for emulation by Bochs have been set."
;; ;;
6) driver="lance"; ;; 7) driver="lance"; ;;
7) driver="psip0"; ;; 8) driver="e1000"; ;;
9) driver="psip0"; ;;
*) warn "choose a number" *) warn "choose a number"
esac esac
} }

44
drivers/e1000/Makefile Normal file
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@ -0,0 +1,44 @@
#
# Makefile for the Intel Pro/1000 driver.
#
DRIVER = e1000
#
# Directories.
#
u = /usr
i = $u/include
s = $i/sys
m = $i/minix
b = $i/ibm
d = ..
#
# Build Programs, Flags and Variables.
#
CC = exec cc
CFLAGS = -I$i $(CPROFILE)
LDFLAGS = -i
LIBS = -lsys -ltimers
OBJ = e1000.o
# build local binary
all build: $(DRIVER)
$(DRIVER): $(OBJ)
$(CC) -o $@ $(LDFLAGS) $(OBJ) $(LIBS)
install -S 128k $(DRIVER)
# install with other drivers
install: /usr/sbin/$(DRIVER)
/usr/sbin/$(DRIVER): $(DRIVER)
install -o root -cs $? $@
# clean up local files
clean:
rm -f *.o $(DRIVER)
depend:
mkdep "$(CC) -E $(CPPFLAGS)" *.c > .depend
# Include generated dependencies.
include .depend

1262
drivers/e1000/e1000.c Normal file
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177
drivers/e1000/e1000.h Normal file
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@ -0,0 +1,177 @@
/**
* @file e1000.h
*
* @brief Device driver implementation declarations for the
* Intel Pro/1000 Gigabit Ethernet card(s).
*
* Parts of this code is based on the DragonflyBSD (FreeBSD)
* implementation, and the fxp driver for Minix 3.
*
* @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/
* @see fxp.c
*
* @author Niek Linnenbank <nieklinnenbank@gmail.com>
* @date September 2009
*
*/
#ifndef __E1000_H
#define __E1000_H
#include "../drivers.h"
#include <stdlib.h>
#include <net/hton.h>
#include <net/gen/ether.h>
#include <net/gen/eth_io.h>
#include <ibm/pci.h>
#include <minix/ds.h>
#include "e1000_hw.h"
/**
* @name Constants.
* @{
*/
/** Maximum number of cards supported. */
#define E1000_PORT_NR 1
/** Number of receive descriptors per card. */
#define E1000_RXDESC_NR 256
/** Number of transmit descriptors per card. */
#define E1000_TXDESC_NR 256
/** Number of I/O vectors to use. */
#define E1000_IOVEC_NR 16
/** Size of each I/O buffer per descriptor. */
#define E1000_IOBUF_SIZE 2048
/** Debug verbosity. */
#define E1000_VERBOSE 1
/** MAC address override variable. */
#define E1000_ENVVAR "E1000ETH"
/**
* @}
*/
/**
* @name Status Flags.
* @{
*/
/** Card has been detected on the PCI bus. */
#define E1000_DETECTED (1 << 0)
/** Card is enabled. */
#define E1000_ENABLED (1 << 1)
/** Client has requested to receive packets. */
#define E1000_READING (1 << 2)
/** Client has requested to write packets. */
#define E1000_WRITING (1 << 3)
/** Received some packets on the card. */
#define E1000_RECEIVED (1 << 4)
/** Transmitted some packets on the card. */
#define E1000_TRANSMIT (1 << 5)
/**
* @}
*/
/**
* @name Macros.
* @{
*/
/**
* @brief Print a debug message.
* @param level Debug verbosity level.
* @param args Arguments to printf().
*/
#define E1000_DEBUG(level, args) \
if ((level) <= E1000_VERBOSE) \
{ \
printf args; \
} \
/**
* Read a byte from flash memory.
* @param e e1000_t pointer.
* @param reg Register offset.
*/
#define E1000_READ_FLASH_REG(e,reg) \
*(u32_t *) (((e)->flash) + (reg))
/**
* Read a 16-bit word from flash memory.
* @param e e1000_t pointer.
* @param reg Register offset.
*/
#define E1000_READ_FLASH_REG16(e,reg) \
*(u16_t *) (((e)->flash) + (reg))
/**
* Write a 16-bit word to flash memory.
* @param e e1000_t pointer.
* @param reg Register offset.
* @param value New value.
*/
#define E1000_WRITE_FLASH_REG(e,reg,value) \
*((u32_t *) (((e)->flash) + (reg))) = (value)
/**
* Write a 16-bit word to flash memory.
* @param e e1000_t pointer.
* @param reg Register offset.
* @param value New value.
*/
#define E1000_WRITE_FLASH_REG16(e,reg,value) \
*((u16_t *) (((e)->flash) + (reg))) = (value)
/**
* @}
*/
/**
* @brief Describes the state of an Intel Pro/1000 card.
*/
typedef struct e1000
{
char name[8]; /**< String containing the device name. */
int status; /**< Describes the card's current state. */
int irq; /**< Interrupt Request Vector. */
int irq_hook; /**< Interrupt Request Vector Hook. */
int revision; /**< Hardware Revision Number. */
u8_t *regs; /**< Memory mapped hardware registers. */
u8_t *flash; /**< Optional flash memory. */
u32_t flash_base_addr; /**< Flash base address. */
ether_addr_t address; /**< Ethernet MAC address. */
u16_t (*eeprom_read)(void *, int reg); /**< Function to read
the EEPROM. */
int eeprom_done_bit; /**< Offset of the EERD.DONE bit. */
int eeprom_addr_off; /**< Offset of the EERD.ADDR field. */
e1000_rx_desc_t *rx_desc; /**< Receive Descriptor table. */
int rx_desc_count; /**< Number of Receive Descriptors. */
char *rx_buffer; /**< Receive buffer returned by malloc(). */
int rx_buffer_size; /**< Size of the receive buffer. */
e1000_tx_desc_t *tx_desc; /**< Transmit Descriptor table. */
int tx_desc_count; /**< Number of Transmit Descriptors. */
char *tx_buffer; /**< Transmit buffer returned by malloc(). */
int tx_buffer_size; /**< Size of the transmit buffer. */
int client; /**< Process ID being served by e1000. */
message rx_message; /**< Read message received from client. */
message tx_message; /**< Write message received from client. */
size_t rx_size; /**< Size of one packet received. */
}
e1000_t;
#endif /* __E1000_H */

174
drivers/e1000/e1000_hw.h Normal file
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@ -0,0 +1,174 @@
/**
* @file e1000.h
*
* @brief Hardware specific datastructures of the Intel
* Pro/1000 Gigabit Ethernet card(s).
*
* Parts of this code is based on the DragonflyBSD (FreeBSD)
* implementation, and the fxp driver for Minix 3.
*
* @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/
* @see fxp.c
*
* @author Niek Linnenbank <nieklinnenbank@gmail.com>
* @date September 2009
*
*/
#ifndef __E1000_HW_H
#define __E1000_HW_H
#include <stdint.h>
/**
* @name Datastructures.
* @{
*/
/**
* @brief Receive Descriptor Format.
*/
typedef struct e1000_rx_desc
{
u32_t buffer; /**< Address of the receive data buffer (64-bit). */
u32_t buffer_h; /**< High 32-bits of the receive data buffer (unused). */
u16_t length; /**< Size of the receive buffer. */
u16_t checksum; /**< Packet checksum. */
u8_t status; /**< Descriptor status. */
u8_t errors; /**< Descriptor errors. */
u16_t special; /**< VLAN information. */
}
e1000_rx_desc_t;
/**
* @brief Transmit Descriptor Format.
*/
typedef struct e1000_tx_desc
{
u32_t buffer; /**< Address of the transmit buffer (64-bit). */
u32_t buffer_h; /**< High 32-bits of the transmit buffer (unused). */
u16_t length; /**< Size of the transmit buffer contents. */
u8_t checksum_off; /**< Checksum Offset. */
u8_t command; /**< Command field. */
u8_t status; /**< Status field. */
u8_t checksum_st; /**< Checksum Start. */
u16_t special; /**< Optional special bits. */
}
e1000_tx_desc_t;
/**
* @brief ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown.
* @see http://gitweb.dragonflybsd.org
*/
union ich8_hws_flash_status
{
struct ich8_hsfsts
{
unsigned flcdone :1; /**< bit 0 Flash Cycle Done */
unsigned flcerr :1; /**< bit 1 Flash Cycle Error */
unsigned dael :1; /**< bit 2 Direct Access error Log */
unsigned berasesz :2; /**< bit 4:3 Sector Erase Size */
unsigned flcinprog :1; /**< bit 5 flash cycle in Progress */
unsigned reserved1 :2; /**< bit 13:6 Reserved */
unsigned reserved2 :6; /**< bit 13:6 Reserved */
unsigned fldesvalid :1; /**< bit 14 Flash Descriptor Valid */
unsigned flockdn :1; /**< bit 15 Flash Config Lock-Down */
} hsf_status;
u16_t regval;
};
/**
* @brief ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown.
* @see http://gitweb.dragonflybsd.org
*/
union ich8_hws_flash_ctrl
{
struct ich8_hsflctl
{
unsigned flcgo :1; /**< 0 Flash Cycle Go */
unsigned flcycle :2; /**< 2:1 Flash Cycle */
unsigned reserved :5; /**< 7:3 Reserved */
unsigned fldbcount :2; /**< 9:8 Flash Data Byte Count */
unsigned flockdn :6; /**< 15:10 Reserved */
} hsf_ctrl;
u16_t regval;
};
/**
* @brief ICH Flash Region Access Permissions.
* @see http://gitweb.dragonflybsd.org
*/
union ich8_hws_flash_regacc
{
struct ich8_flracc
{
unsigned grra :8; /**< 0:7 GbE region Read Access */
unsigned grwa :8; /**< 8:15 GbE region Write Access */
unsigned gmrag :8; /**< 23:16 GbE Master Read Access Grant */
unsigned gmwag :8; /**< 31:24 GbE Master Write Access Grant */
} hsf_flregacc;
u16_t regval;
};
/**
* @}
*/
/**
* @name Receive Status Field Bits.
* @{
*/
/** Passed In-exact Filter. */
#define E1000_RX_STATUS_PIF (1 << 7)
/** End of Packet. */
#define E1000_RX_STATUS_EOP (1 << 1)
/** Descriptor Done. */
#define E1000_RX_STATUS_DONE (1 << 0)
/**
* @}
*/
/**
* @name Receive Errors Field Bits.
* @{
*/
/** RX Data Error. */
#define E1000_RX_ERROR_RXE (1 << 7)
/** Carrier Extension Error. */
#define E1000_RX_ERROR_CXE (1 << 4)
/** Sequence/Framing Error. */
#define E1000_RX_ERROR_SEQ (1 << 2)
/** CRC/Alignment Error. */
#define E1000_RX_ERROR_CE (1 << 0)
/**
* @}
*/
/**
* @name Transmit Command Field Bits.
* @{
*/
/** End of Packet. */
#define E1000_TX_CMD_EOP (1 << 0)
/** Insert FCS/CRC. */
#define E1000_TX_CMD_FCS (1 << 1)
/** Report Status. */
#define E1000_TX_CMD_RS (1 << 3)
/**
* @}
*/
#endif /* __E1000_HW_H */

137
drivers/e1000/e1000_pci.h Normal file
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@ -0,0 +1,137 @@
/**
* @file e1000_pci.h
*
* @brief PCI Device Identity numbers of Intel Pro/1000
* Gigabit Ethernet cards.
*
* Parts of this code is based on the DragonflyBSD (FreeBSD)
* implementation, and the fxp driver for Minix 3.
*
* @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/
* @see fxp.c
*
* @author Niek Linnenbank <nieklinnenbank@gmail.com>
* @date September 2009
*
*/
#ifndef __E1000_PCI_H
#define __E1000_PCI_H
/**
* @name PCI Device ID's.
* @{
*/
#define E1000_DEV_ID_82542 0x1000
#define E1000_DEV_ID_82543GC_FIBER 0x1001
#define E1000_DEV_ID_82543GC_COPPER 0x1004
#define E1000_DEV_ID_82544EI_COPPER 0x1008
#define E1000_DEV_ID_82544EI_FIBER 0x1009
#define E1000_DEV_ID_82544GC_COPPER 0x100C
#define E1000_DEV_ID_82544GC_LOM 0x100D
#define E1000_DEV_ID_82540EM 0x100E
#define E1000_DEV_ID_82540EM_LOM 0x1015
#define E1000_DEV_ID_82540EP_LOM 0x1016
#define E1000_DEV_ID_82540EP 0x1017
#define E1000_DEV_ID_82540EP_LP 0x101E
#define E1000_DEV_ID_82545EM_COPPER 0x100F
#define E1000_DEV_ID_82545EM_FIBER 0x1011
#define E1000_DEV_ID_82545GM_COPPER 0x1026
#define E1000_DEV_ID_82545GM_FIBER 0x1027
#define E1000_DEV_ID_82545GM_SERDES 0x1028
#define E1000_DEV_ID_82546EB_COPPER 0x1010
#define E1000_DEV_ID_82546EB_FIBER 0x1012
#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
#define E1000_DEV_ID_82546GB_COPPER 0x1079
#define E1000_DEV_ID_82546GB_FIBER 0x107A
#define E1000_DEV_ID_82546GB_SERDES 0x107B
#define E1000_DEV_ID_82546GB_PCIE 0x108A
#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099
#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
#define E1000_DEV_ID_82541EI 0x1013
#define E1000_DEV_ID_82541EI_MOBILE 0x1018
#define E1000_DEV_ID_82541ER_LOM 0x1014
#define E1000_DEV_ID_82541ER 0x1078
#define E1000_DEV_ID_82541GI 0x1076
#define E1000_DEV_ID_82541GI_LF 0x107C
#define E1000_DEV_ID_82541GI_MOBILE 0x1077
#define E1000_DEV_ID_82547EI 0x1019
#define E1000_DEV_ID_82547EI_MOBILE 0x101A
#define E1000_DEV_ID_82547GI 0x1075
#define E1000_DEV_ID_82571EB_COPPER 0x105E
#define E1000_DEV_ID_82571EB_FIBER 0x105F
#define E1000_DEV_ID_82571EB_SERDES 0x1060
#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
#define E1000_DEV_ID_82572EI_COPPER 0x107D
#define E1000_DEV_ID_82572EI_FIBER 0x107E
#define E1000_DEV_ID_82572EI_SERDES 0x107F
#define E1000_DEV_ID_82572EI 0x10B9
#define E1000_DEV_ID_82573E 0x108B
#define E1000_DEV_ID_82573E_IAMT 0x108C
#define E1000_DEV_ID_82573L 0x109A
#define E1000_DEV_ID_82574L 0x10D3
#define E1000_DEV_ID_82574LA 0x10F6
#define E1000_DEV_ID_82583V 0x150C
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
#define E1000_DEV_ID_ICH8_IGP_C 0x104B
#define E1000_DEV_ID_ICH8_IFE 0x104C
#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
#define E1000_DEV_ID_ICH8_IGP_M 0x104D
#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
#define E1000_DEV_ID_ICH9_BM 0x10E5
#define E1000_DEV_ID_ICH9_IGP_C 0x294C
#define E1000_DEV_ID_ICH9_IFE 0x10C0
#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
#define E1000_DEV_ID_82576 0x10C9
#define E1000_DEV_ID_82576_FIBER 0x10E6
#define E1000_DEV_ID_82576_SERDES 0x10E7
#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
#define E1000_DEV_ID_82576_NS 0x150A
#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
#define E1000_DEV_ID_82575EB_COPPER 0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
#define E1000_DEV_ID_82575GB_QUAD_COPPER_PM 0x10E2
/**
* @}
*/
/**
* @name Revision Numbers.
* @{
*/
#define E1000_DEV_RID_82540 0x03
#define E1000_DEV_RID_82541 0x05
/**
* @}
*/
#endif /* __E1000_PCI_H */

310
drivers/e1000/e1000_reg.h Normal file
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/**
* @file e1000_reg.h
*
* @brief Hardware specific registers and flags of the Intel
* Pro/1000 Gigabit Ethernet card(s).
*
* Parts of this code is based on the DragonflyBSD (FreeBSD)
* implementation, and the fxp driver for Minix 3.
*
* @see http://svn.freebsd.org/viewvc/base/head/sys/dev/e1000/
* @see fxp.c
*
* @author Niek Linnenbank <nieklinnenbank@gmail.com>
* @date September 2009
*
*/
#ifndef __E1000_REG_H
#define __E1000_REG_H
/**
* @name Controller Registers.
* @{
*/
/** Device Control. */
#define E1000_REG_CTRL 0x00000
/** Device Status. */
#define E1000_REG_STATUS 0x00008
/** EEPROM Read. */
#define E1000_REG_EERD 0x00014
/** Flow Control Address Low. */
#define E1000_REG_FCAL 0x00028
/** Flow Control Address High. */
#define E1000_REG_FCAH 0x0002c
/** Flow Control Type. */
#define E1000_REG_FCT 0x00030
/** Interrupt Cause Read. */
#define E1000_REG_ICR 0x000c0
/** Interrupt Mask Set/Read Register. */
#define E1000_REG_IMS 0x000d0
/** Receive Control Register. */
#define E1000_REG_RCTL 0x00100
/** Transmit Control Register. */
#define E1000_REG_TCTL 0x00400
/** Flow Control Transmit Timer Value. */
#define E1000_REG_FCTTV 0x00170
/** Receive Descriptor Base Address Low. */
#define E1000_REG_RDBAL 0x02800
/** Receive Descriptor Base Address High. */
#define E1000_REG_RDBAH 0x02804
/** Receive Descriptor Length. */
#define E1000_REG_RDLEN 0x02808
/** Receive Descriptor Head. */
#define E1000_REG_RDH 0x02810
/** Receive Descriptor Tail. */
#define E1000_REG_RDT 0x02818
/** Transmit Descriptor Base Address Low. */
#define E1000_REG_TDBAL 0x03800
/** Transmit Descriptor Base Address High. */
#define E1000_REG_TDBAH 0x03804
/** Transmit Descriptor Length. */
#define E1000_REG_TDLEN 0x03808
/** Transmit Descriptor Head. */
#define E1000_REG_TDH 0x03810
/** Transmit Descriptor Tail. */
#define E1000_REG_TDT 0x03818
/** CRC Error Count. */
#define E1000_REG_CRCERRS 0x04000
/** RX Error Count. */
#define E1000_REG_RXERRC 0x0400c
/** Missed Packets Count. */
#define E1000_REG_MPC 0x04010
/** Collision Count. */
#define E1000_REG_COLC 0x04028
/** Total Packets Received. */
#define E1000_REG_TPR 0x040D0
/** Total Packets Transmitted. */
#define E1000_REG_TPT 0x040D4
/** Receive Address Low. */
#define E1000_REG_RAL 0x05400
/** Receive Address High. */
#define E1000_REG_RAH 0x05404
/** Multicast Table Array. */
#define E1000_REG_MTA 0x05200
/**
* @}
*/
/**
* @name Control Register Bits.
* @{
*/
/** Auto-Speed Detection Enable. */
#define E1000_REG_CTRL_ASDE (1 << 5)
/** Link Reset. */
#define E1000_REG_CTRL_LRST (1 << 3)
/** Set Link Up. */
#define E1000_REG_CTRL_SLU (1 << 6)
/** Invert Los Of Signal. */
#define E1000_REG_CTRL_ILOS (1 << 7)
/** Device Reset. */
#define E1000_REG_CTRL_RST (1 << 26)
/** VLAN Mode Enable. */
#define E1000_REG_CTRL_VME (1 << 30)
/** PHY Reset. */
#define E1000_REG_CTRL_PHY_RST (1 << 31)
/**
* @}
*/
/**
* @name Status Register Bits.
* @{
*/
/** Link Full Duplex Configuration Indication. */
#define E1000_REG_STATUS_FD (1 << 0)
/** Link Up Indication. */
#define E1000_REG_STATUS_LU (1 << 1)
/** Transmission Paused. */
#define E1000_REG_STATUS_TXOFF (1 << 4)
/** Link Speed Setting. */
#define E1000_REG_STATUS_SPEED ((1 << 6) | (1 << 7))
/**
* @}
*/
/**
* @name EEPROM Read Register Bits.
* @{
*/
/** Start Read. */
#define E1000_REG_EERD_START (1 << 0)
/** Read Done. */
#define E1000_REG_EERD_DONE (1 << 4)
/** Read Address Bit Mask. */
#define E1000_REG_EERD_ADDR (0xff << 8)
/** Read Data Bit Mask. */
#define E1000_REG_EERD_DATA (0xffff << 16)
/**
* @}
*/
/**
* @name Interrupt Cause Read.
* @{
*/
/** Transmit Descripts Written Back. */
#define E1000_REG_ICR_TXDW (1 << 0)
/** Transmit Queue Empty. */
#define E1000_REG_ICR_TXQE (1 << 1)
/** Link Status Change. */
#define E1000_REG_ICR_LSC (1 << 2)
/** Receiver Overrun. */
#define E1000_REG_ICR_RXO (1 << 6)
/** Receiver Timer Interrupt. */
#define E1000_REG_ICR_RXT (1 << 7)
/**
* @}
*/
/**
* @name Interrupt Mask Set/Read Register Bits.
* @{
*/
/** Transmit Descripts Written Back. */
#define E1000_REG_IMS_TXDW (1 << 0)
/** Transmit Queue Empty. */
#define E1000_REG_IMS_TXQE (1 << 1)
/** Link Status Change. */
#define E1000_REG_IMS_LSC (1 << 2)
/** Receiver FIFO Overrun. */
#define E1000_REG_IMS_RXO (1 << 6)
/** Receiver Timer Interrupt. */
#define E1000_REG_IMS_RXT (1 << 7)
/**
* @}
*/
/**
* @name Receive Control Register Bits.
* @{
*/
/** Receive Enable. */
#define E1000_REG_RCTL_EN (1 << 1)
/** Multicast Promiscious Enable. */
#define E1000_REG_RCTL_MPE (1 << 4)
/** Broadcast Accept Mode. */
#define E1000_REG_RCTL_BAM (1 << 15)
/** Receive Buffer Size. */
#define E1000_REG_RCTL_BSIZE ((1 << 16) | (1 << 17))
/**
* @}
*/
/**
* @name Transmit Control Register Bits.
* @{
*/
/** Transmit Enable. */
#define E1000_REG_TCTL_EN (1 << 1)
/** Pad Short Packets. */
#define E1000_REG_TCTL_PSP (1 << 3)
/**
* @}
*/
/**
* @name Receive Address High Register Bits.
* @{
*/
/** Receive Address Valid. */
#define E1000_REG_RAH_AV (1 << 31)
/**
* @}
*/
/**
* @name ICH Flash Registers.
* @see http://gitweb.dragonflybsd.org
* @{
*/
#define ICH_FLASH_GFPREG 0x0000
#define ICH_FLASH_HSFSTS 0x0004
#define ICH_FLASH_HSFCTL 0x0006
#define ICH_FLASH_FADDR 0x0008
#define ICH_FLASH_FDATA0 0x0010
#define FLASH_GFPREG_BASE_MASK 0x1FFF
#define FLASH_SECTOR_ADDR_SHIFT 12
#define ICH_FLASH_READ_COMMAND_TIMEOUT 500
#define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
#define ICH_CYCLE_READ 0
#define ICH_FLASH_CYCLE_REPEAT_COUNT 10
/**
* @}
*/
#endif /* __E1000_REG_H */

3
drivers/pci/pci_table.c
View file

@ -129,10 +129,13 @@ struct pci_device pci_device_table[]=
{ 0x5333, 0x88d0, "S3 Vision 964 vers 0" }, { 0x5333, 0x88d0, "S3 Vision 964 vers 0" },
{ 0x5333, 0x8a01, "S3 Virge/DX or /GX" }, { 0x5333, 0x8a01, "S3 Virge/DX or /GX" },
{ 0x8086, 0x1004, "Intel 82543GC Gigabit Ethernet Controller" }, { 0x8086, 0x1004, "Intel 82543GC Gigabit Ethernet Controller" },
{ 0x8086, 0x100E, "Intel PRO/1000 MT Desktop Adapter" },
{ 0x8086, 0x1029, "Intel EtherExpressPro100 ID1029" }, { 0x8086, 0x1029, "Intel EtherExpressPro100 ID1029" },
{ 0x8086, 0x1030, "Intel Corporation 82559 InBusiness 10/100" }, { 0x8086, 0x1030, "Intel Corporation 82559 InBusiness 10/100" },
{ 0x8086, 0x103d, "Intel Corporation 82801DB PRO/100 VE (MOB)" }, { 0x8086, 0x103d, "Intel Corporation 82801DB PRO/100 VE (MOB)" },
{ 0x8086, 0x1064, "Intel Corporation 82562 PRO/100 VE" }, { 0x8086, 0x1064, "Intel Corporation 82562 PRO/100 VE" },
{ 0x8086, 0x107C, "Intel PRO/1000 GT Desktop Adapter" },
{ 0x8086, 0x10CD, "Intel PRO/1000 Gigabit Network Connection" },
{ 0x8086, 0x1209, "Intel EtherExpressPro100 82559ER" }, { 0x8086, 0x1209, "Intel EtherExpressPro100 82559ER" },
{ 0x8086, 0x1229, "Intel EtherExpressPro100 82557/8/9" }, { 0x8086, 0x1229, "Intel EtherExpressPro100 82557/8/9" },
{ 0x8086, 0x122D, "Intel 82437FX" }, { 0x8086, 0x122D, "Intel 82437FX" },

22
etc/drivers.conf
View file

@ -517,3 +517,25 @@ driver filter
bios_wini bios_wini
; ;
}; };
driver e1000
{
system
UMAP # 14
IRQCTL # 19
DEVIO # 21
SETALARM # 24
TIMES # 25
GETINFO # 26
SAFECOPYFROM # 31
SAFECOPYTO # 32
SETGRANT # 34
SYSCTL
;
pci device 8086/100e;
pci device 8086/107c;
pci device 8086/10cd;
ipc
SYSTEM PM RS LOG TTY DS VM
pci inet ;
};

2
etc/usr/rc
View file

@ -91,7 +91,7 @@ start)
fi fi
# start only network drivers that are in use # start only network drivers that are in use
for driver in lance rtl8139 rtl8169 fxp dpeth dp8390 orinoco for driver in lance rtl8139 rtl8169 fxp e1000 dpeth dp8390 orinoco
do do
if grep " $driver " /etc/inet.conf > /dev/null 2>&1 if grep " $driver " /etc/inet.conf > /dev/null 2>&1
then then