Print PCI capability types.
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2 changed files with 49 additions and 1 deletions
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@ -144,6 +144,7 @@ FORWARD _PROTOTYPE( void pcii_wreg32, (int busind, int devind, int port,
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u32_t value) );
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u32_t value) );
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FORWARD _PROTOTYPE( u16_t pcii_rsts, (int busind) );
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FORWARD _PROTOTYPE( u16_t pcii_rsts, (int busind) );
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FORWARD _PROTOTYPE( void pcii_wsts, (int busind, U16_t value) );
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FORWARD _PROTOTYPE( void pcii_wsts, (int busind, U16_t value) );
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FORWARD _PROTOTYPE( void print_capabilities, (int devind) );
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/*===========================================================================*
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/*===========================================================================*
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* helper functions for I/O *
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* helper functions for I/O *
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@ -798,6 +799,9 @@ printf("probe_bus(%d)\n", busind);
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break;
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break;
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}
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}
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if (debug)
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print_capabilities(devind);
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if (nr_pcidev >= NR_PCIDEV)
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if (nr_pcidev >= NR_PCIDEV)
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panic("PCI","too many PCI devices", nr_pcidev);
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panic("PCI","too many PCI devices", nr_pcidev);
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devind= nr_pcidev;
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devind= nr_pcidev;
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@ -2209,6 +2213,45 @@ u16_t value;
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#endif
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#endif
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}
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}
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/*===========================================================================*
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* print_capabilities *
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*===========================================================================*/
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PRIVATE void print_capabilities(devind)
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int devind;
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{
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u8_t status, capptr, type, next;
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char *str;
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/* Check capabilities bit in the device status register */
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status= pci_attr_r16(devind, PCI_SR);
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if (!(status & PSR_CAPPTR))
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return;
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capptr= (pci_attr_r8(devind, PCI_CAPPTR) & PCI_CP_MASK);
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while (capptr != 0)
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{
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type = pci_attr_r8(devind, capptr+CAP_TYPE);
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next= (pci_attr_r8(devind, capptr+CAP_NEXT) & PCI_CP_MASK);
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switch(type)
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{
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case 1: str= "PCI Power Management"; break;
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case 2: str= "AGP"; break;
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case 3: str= "Vital Product Data"; break;
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case 4: str= "Slot Identification"; break;
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case 5: str= "Message Signaled Interrupts"; break;
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case 6: str= "CompactPCI Hot Swap"; break;
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case 8: str= "AMD HyperTransport"; break;
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case 0xf: str= "AMD I/O MMU"; break;
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defuault: str= "(unknown type)"; break;
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}
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printf(" @0x%x: capability type 0x%x: %s\n",
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capptr, type, str);
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capptr= next;
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}
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}
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/*
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/*
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* $PchId: pci.c,v 1.7 2003/08/07 09:06:51 philip Exp $
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* $PchId: pci.c,v 1.7 2003/08/07 09:06:51 philip Exp $
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*/
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*/
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@ -14,6 +14,7 @@ Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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#define PSR_SSE 0x4000 /* Signaled System Error */
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#define PSR_SSE 0x4000 /* Signaled System Error */
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#define PSR_RMAS 0x2000 /* Received Master Abort Status */
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#define PSR_RMAS 0x2000 /* Received Master Abort Status */
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#define PSR_RTAS 0x1000 /* Received Target Abort Status */
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#define PSR_RTAS 0x1000 /* Received Target Abort Status */
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#define PSR_CAPPTR 0x0010 /* Capabilities list */
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#define PCI_REV 0x08 /* Revision ID */
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#define PCI_REV 0x08 /* Revision ID */
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#define PCI_PIFR 0x09 /* Prog. Interface Register */
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#define PCI_PIFR 0x09 /* Prog. Interface Register */
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#define PCI_SCR 0x0A /* Sub-Class Register */
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#define PCI_SCR 0x0A /* Sub-Class Register */
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@ -41,6 +42,7 @@ Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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#define PCI_SUBDID 0x2E /* Subsystem Device ID */
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#define PCI_SUBDID 0x2E /* Subsystem Device ID */
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#define PCI_EXPROM 0x30 /* Expansion ROM Base Address */
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#define PCI_EXPROM 0x30 /* Expansion ROM Base Address */
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#define PCI_CAPPTR 0x34 /* Capabilities Pointer */
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#define PCI_CAPPTR 0x34 /* Capabilities Pointer */
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#define PCI_CP_MASK 0xfc /* Lower 2 bits should be ignored */
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#define PCI_ILR 0x3C /* Interrupt Line Register */
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#define PCI_ILR 0x3C /* Interrupt Line Register */
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#define PCI_ILR_UNKNOWN 0xFF /* IRQ is unassigned or unknown */
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#define PCI_ILR_UNKNOWN 0xFF /* IRQ is unassigned or unknown */
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#define PCI_IPR 0x3D /* Interrupt Pin Register */
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#define PCI_IPR 0x3D /* Interrupt Pin Register */
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@ -102,6 +104,9 @@ Created: Jan 2000 by Philip Homburg <philip@cs.vu.nl>
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#define CBB_BC_INTEXCA 0x80 /* Interrupt are routed to ExCAs */
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#define CBB_BC_INTEXCA 0x80 /* Interrupt are routed to ExCAs */
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#define CBB_BC_CRST 0x40 /* Assert reset line */
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#define CBB_BC_CRST 0x40 /* Assert reset line */
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#define CAP_TYPE 0x00 /* Type field in capability */
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#define CAP_NEXT 0x01 /* Next field in capability */
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/* Device type values as ([PCI_BCR] << 16) | ([PCI_SCR] << 8) | [PCI_PIFR] */
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/* Device type values as ([PCI_BCR] << 16) | ([PCI_SCR] << 8) | [PCI_PIFR] */
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#define PCI_T3_PCI2PCI 0x060400 /* PCI-to-PCI Bridge device */
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#define PCI_T3_PCI2PCI 0x060400 /* PCI-to-PCI Bridge device */
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#define PCI_T3_PCI2PCI_SUBTR 0x060401 /* Subtr. PCI-to-PCI Bridge */
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#define PCI_T3_PCI2PCI_SUBTR 0x060401 /* Subtr. PCI-to-PCI Bridge */
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