From 0d02dc9d54b9231988ca8b88036ad440473622e2 Mon Sep 17 00:00:00 2001
From: Kees Jongenburger <kees.jongenburger@gmail.com>
Date: Wed, 25 Sep 2013 11:12:46 +0200
Subject: [PATCH] arm:make the MMU fetch pagetable data through the caches.

Change-Id: Ibd7b66558c369d0c0792c02801562580d255fa1f
---
 include/arch/earm/include/vm.h     | 15 +++++++++++++++
 kernel/arch/earm/include/cpufunc.h | 10 +++++++---
 kernel/arch/earm/memory.c          |  2 +-
 3 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/include/arch/earm/include/vm.h b/include/arch/earm/include/vm.h
index 98c155fc4..0d7cec642 100644
--- a/include/arch/earm/include/vm.h
+++ b/include/arch/earm/include/vm.h
@@ -163,6 +163,21 @@ arm/vm.h
 #define ARM_VM_PFE_FS4    (1<<10)  /* Fault status (bit 4) */
 #define ARM_VM_PFE_FS3_0   0xf     /* Fault status (bits 3:0) */
 
+
+/* Translation table base register specfic flags */
+#define ARM_TTBR_C (0x01) /* Cacheable bit. Indicates whether the translation table walk is to Inner Cacheable memory. */
+
+/* RGN bits[4:3] indicates the Outer cacheability attributes 
+   for the memory associated with the translation table walks */
+#define ARM_TTBR_OUTER_NC    (0x0 << 3) /* Non-cacheable*/
+#define ARM_TTBR_OUTER_WBWA  (0x1 << 3) /* Outer Write-Back Write-Allocate Cacheable. */
+#define ARM_TTBR_OUTER_WT    (0x2 << 3) /* Outer Write-Through Cacheable. */
+#define ARM_TTBR_OUTER_WBNWA (0x3 << 3) /* Outer Write-Back no Write-Allocate Cacheable. */
+
+
+#define ARM_TTBR_ADDR_MASK (0xffffc000) /* only the 18 upper bits are to be used as address */
+#define ARM_TTBR_FLAGS_CACHED ARM_TTBR_OUTER_WBWA
+
 /* Fault status */
 #define ARM_VM_PFE_FS(s) \
     ((((s) & ARM_VM_PFE_FS4) >> 6) | ((s) & ARM_VM_PFE_FS3_0))
diff --git a/kernel/arch/earm/include/cpufunc.h b/kernel/arch/earm/include/cpufunc.h
index d44f505b3..c5606dbe4 100644
--- a/kernel/arch/earm/include/cpufunc.h
+++ b/kernel/arch/earm/include/cpufunc.h
@@ -215,16 +215,20 @@ static inline u32_t read_ttbr0()
 	asm volatile("mrc p15, 0, %[bar], c2, c0, 0 @ Read TTBR0\n\t"
 			: [bar] "=r" (bar));
 
-	return bar;
+	return bar & ARM_TTBR_ADDR_MASK;
 }
 
 /* Write Translation Table Base Register 0 */
 static inline void write_ttbr0(u32_t bar)
 {
 	barrier();
-
+	/* In our setup TTBR contains the base address *and* the flags
+	   but other pieces of the kernel code expect ttbr to be the 
+	   base address of the l1 page table. We therefore add the
+	   flags here and remove them in the read_ttbr0 */
+	u32_t v  =  (bar  & ARM_TTBR_ADDR_MASK ) | ARM_TTBR_FLAGS_CACHED;
 	asm volatile("mcr p15, 0, %[bar], c2, c0, 0 @ Write TTBR0\n\t"
-			: : [bar] "r" (bar));
+			: : [bar] "r" (v));
 
 	refresh_tlb();
 }
diff --git a/kernel/arch/earm/memory.c b/kernel/arch/earm/memory.c
index ad61ace38..fa6fb1344 100644
--- a/kernel/arch/earm/memory.c
+++ b/kernel/arch/earm/memory.c
@@ -303,7 +303,7 @@ int vm_lookup(const struct proc *proc, const vir_bytes virtual,
 	assert(HASPT(proc));
 
 	/* Retrieve page directory entry. */
-	root = (u32_t *) proc->p_seg.p_ttbr;
+	root = (u32_t *) (proc->p_seg.p_ttbr & ARM_TTBR_ADDR_MASK);
 	assert(!((u32_t) root % ARM_PAGEDIR_SIZE));
 	pde = ARM_VM_PDE(virtual);
 	assert(pde >= 0 && pde < ARM_VM_DIR_ENTRIES);