Add cttybaud boot monitor variable to control speed of serial console (combine with ctty 0)
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5f1ab506c8
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03a7d0e8ae
5 changed files with 70 additions and 10 deletions
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@ -158,6 +158,7 @@
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#define INVAL_GID ((gid_t) -1) /* invalid gid value */
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#define SERVARNAME "cttyline"
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#define SERBAUDVARNAME "cttybaud"
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/* Bits for the system property flags in boot image processes. */
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#define PROC_FULLVM 0x100 /* VM sets and manages full pagetable */
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@ -53,6 +53,9 @@ FORWARD _PROTOTYPE( void ser_debug, (int c));
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#ifdef CONFIG_SMP
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FORWARD _PROTOTYPE( void ser_dump_proc_cpu, (void));
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#endif
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#if !CONFIG_OXPCIE
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FORWARD _PROTOTYPE( void ser_init, (void));
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#endif
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PUBLIC __dead void arch_monitor(void)
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{
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@ -371,6 +374,10 @@ PUBLIC void arch_init(void)
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tss_init(0, get_k_stack_top(0));
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#endif
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#if !CONFIG_OXPCIE
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ser_init();
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#endif
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acpi_init();
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#if defined(CONFIG_APIC) && !defined(CONFIG_SMP)
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@ -719,3 +726,30 @@ PUBLIC void fpu_sigcontext(struct proc *pr, struct sigframe *fr, struct sigconte
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* FPE_INTDIV */
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}
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}
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#if !CONFIG_OXPCIE
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PRIVATE void ser_init(void)
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{
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unsigned char lcr;
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unsigned divisor;
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/* keep BIOS settings if cttybaud is not set */
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if (serial_debug_baud <= 0) return;
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/* set DLAB to make baud accessible */
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lcr = LCR_8BIT | LCR_1STOP | LCR_NPAR;
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outb(COM1_LCR, lcr | LCR_DLAB);
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/* set baud rate */
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divisor = UART_BASE_FREQ / serial_debug_baud;
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if (divisor < 1) divisor = 1;
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if (divisor > 65535) divisor = 65535;
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outb(COM1_DLL, divisor & 0xff);
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outb(COM1_DLM, (divisor >> 8) & 0xff);
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/* clear DLAB */
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outb(COM1_LCR, lcr);
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}
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#endif
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@ -2,19 +2,37 @@
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#ifndef _KERN_SERIAL_H
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#define _KERN_SERIAL_H 1
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#define THRREG 0
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#define RBRREG 0
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#define FICRREG 2
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#define LSRREG 5
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#define LCRREG 3
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#define THRREG 0 /* transmitter holding, write-only, DLAB must be clear */
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#define RBRREG 0 /* receiver buffer, read-only, DLAB must be clear */
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#define DLLREG 0 /* divisor latch LSB, read/write, DLAB must be set */
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#define DLMREG 1 /* divisor latch MSB, read/write, DLAB must be set */
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#define FICRREG 2 /* FIFO control, write-only */
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#define LCRREG 3 /* line control, read/write */
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#define LSRREG 5 /* line status, read-only */
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#define SPRREG 7
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#define COM1_BASE 0x3F8
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#define COM1_THR (COM1_BASE + THRREG)
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#define COM1_RBR (COM1_BASE + RBRREG)
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#define COM1_LSR (COM1_BASE + LSRREG)
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#define COM1_BASE 0x3F8
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#define COM1_THR (COM1_BASE + THRREG)
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#define COM1_RBR (COM1_BASE + RBRREG)
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#define COM1_DLL (COM1_BASE + DLLREG)
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#define COM1_DLM (COM1_BASE + DLMREG)
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#define COM1_LCR (COM1_BASE + LCRREG)
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#define LCR_5BIT 0x00 /* 5 bits per data word */
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#define LCR_6BIT 0x01 /* 6 bits per data word */
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#define LCR_7BIT 0x02 /* 7 bits per data word */
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#define LCR_8BIT 0x03 /* 8 bits per data word */
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#define LCR_1STOP 0x00 /* 1/1.5 stop bits */
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#define LCR_2STOP 0x04 /* 2 stop bits */
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#define LCR_NPAR 0x00 /* no parity */
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#define LCR_OPAR 0x08 /* odd parity */
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#define LCR_EPAR 0x18 /* even parity */
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#define LCR_BREAK 0x40 /* enable break */
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#define LCR_DLAB 0x80 /* access DLAB registers */
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#define COM1_LSR (COM1_BASE + LSRREG)
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#define LSR_DR 0x01
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#define LSR_THRE 0x20
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#define LCR_DLA 0x80
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#define UART_BASE_FREQ 115200U
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#endif
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@ -42,6 +42,7 @@ EXTERN u32_t system_hz; /* HZ value */
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EXTERN reg_t mon_sp; /* boot monitor stack */
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EXTERN int mon_return; /* true if we can return to monitor */
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EXTERN int do_serial_debug;
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EXTERN int serial_debug_baud;
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EXTERN time_t boottime;
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EXTERN char params_buffer[512]; /* boot monitor parameters */
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EXTERN int minix_panicing;
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@ -83,10 +83,16 @@ PUBLIC void cstart(
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system_hz = atoi(value);
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if(!value || system_hz < 2 || system_hz > 50000) /* sanity check */
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system_hz = DEFAULT_HZ;
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/* Intitialize serial debugging */
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value = env_get(SERVARNAME);
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if(value && atoi(value) == 0)
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if(value && atoi(value) == 0) {
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do_serial_debug=1;
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value = env_get(SERBAUDVARNAME);
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if (value) serial_debug_baud = atoi(value);
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}
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#ifdef CONFIG_APIC
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value = env_get("no_apic");
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if(value)
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