153 lines
4.7 KiB
C
153 lines
4.7 KiB
C
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#ifndef _OMAP_I2C_REGISTERS_H
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#define _OMAP_I2C_REGISTERS_H
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/* I2C Addresses for am335x (BeagleBone White / BeagleBone Black) */
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/* IRQ Numbers */
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#define AM335X_I2C0_IRQ 70
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#define AM335X_I2C1_IRQ 71
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#define AM335X_I2C2_IRQ 30
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/* Base Addresses */
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#define AM335X_I2C0_BASE 0x44e0b000
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#define AM335X_I2C1_BASE 0x4802a000
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#define AM335X_I2C2_BASE 0x4819c000
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/* Size of I2C Register Address Range */
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#define AM335X_I2C0_SIZE 0x1000
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#define AM335X_I2C1_SIZE 0x1000
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#define AM335X_I2C2_SIZE 0x1000
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/* Register Offsets */
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#define AM335X_I2C_REVNB_LO 0x00
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#define AM335X_I2C_REVNB_HI 0x04
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#define AM335X_I2C_SYSC 0x10
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#define AM335X_I2C_IRQSTATUS_RAW 0x24
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#define AM335X_I2C_IRQSTATUS 0x28
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#define AM335X_I2C_IRQENABLE_SET 0x2c
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#define AM335X_I2C_IRQENABLE_CLR 0x30
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#define AM335X_I2C_WE 0x34
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#define AM335X_I2C_DMARXENABLE_SET 0x38
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#define AM335X_I2C_DMATXENABLE_SET 0x3c
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#define AM335X_I2C_DMARXENABLE_CLR 0x40
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#define AM335X_I2C_DMATXENABLE_CLR 0x44
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#define AM335X_I2C_DMARXWAKE_EN 0x48
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#define AM335X_I2C_DMATXWAKE_EN 0x4c
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#define AM335X_I2C_SYSS 0x90
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#define AM335X_I2C_BUF 0x94
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#define AM335X_I2C_CNT 0x98
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#define AM335X_I2C_DATA 0x9c
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#define AM335X_I2C_CON 0xa4
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#define AM335X_I2C_OA 0xa8
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#define AM335X_I2C_SA 0xac
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#define AM335X_I2C_PSC 0xb0
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#define AM335X_I2C_SCLL 0xb4
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#define AM335X_I2C_SCLH 0xb8
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#define AM335X_I2C_SYSTEST 0xbc
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#define AM335X_I2C_BUFSTAT 0xc0
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#define AM335X_I2C_OA1 0xc4
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#define AM335X_I2C_OA2 0xc8
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#define AM335X_I2C_OA3 0xcc
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#define AM335X_I2C_ACTOA 0xd0
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#define AM335X_I2C_SBLOCK 0xd4
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/* Constants */
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#define AM335X_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */
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#define AM335X_MODULE_CLOCK 12000000 /* 12 MHz */
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/* I2C_REV value found on the BeagleBone / BeagleBone Black */
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#define AM335X_REV_MAJOR 0x00
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#define AM335X_REV_MINOR 0x0b
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/* I2C Addresses for dm37xx (BeagleBoard-xM) */
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/* IRQ Numbers */
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#define DM37XX_I2C0_IRQ 56
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#define DM37XX_I2C1_IRQ 57
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#define DM37XX_I2C2_IRQ 61
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/* Base Addresses */
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#define DM37XX_I2C0_BASE 0x48070000
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#define DM37XX_I2C1_BASE 0x48072000
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#define DM37XX_I2C2_BASE 0x48060000
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/* Size of I2C Register Address Range */
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#define DM37XX_I2C0_SIZE 0x1000
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#define DM37XX_I2C1_SIZE 0x1000
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#define DM37XX_I2C2_SIZE 0x1000
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/* Register Offsets */
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#define DM37XX_I2C_REV 0x00
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#define DM37XX_I2C_IE 0x04
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#define DM37XX_I2C_STAT 0x08
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#define DM37XX_I2C_WE 0x0C
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#define DM37XX_I2C_SYSS 0x10
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#define DM37XX_I2C_BUF 0x14
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#define DM37XX_I2C_CNT 0x18
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#define DM37XX_I2C_DATA 0x1c
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#define DM37XX_I2C_SYSC 0x20
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#define DM37XX_I2C_CON 0x24
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#define DM37XX_I2C_OA0 0x28
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#define DM37XX_I2C_SA 0x2c
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#define DM37XX_I2C_PSC 0x30
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#define DM37XX_I2C_SCLL 0x34
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#define DM37XX_I2C_SCLH 0x38
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#define DM37XX_I2C_SYSTEST 0x3c
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#define DM37XX_I2C_BUFSTAT 0x40
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#define DM37XX_I2C_OA1 0x44
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#define DM37XX_I2C_OA2 0x48
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#define DM37XX_I2C_OA3 0x4c
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#define DM37XX_I2C_ACTOA 0x50
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#define DM37XX_I2C_SBLOCK 0x54
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/* Constants */
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#define DM37XX_FUNCTIONAL_CLOCK 96000000 /* 96 MHz */
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#define DM37XX_MODULE_CLOCK 19200000 /* 19.2 MHz */
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#define DM37XX_REV_MAJOR 0x04
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#define DM37XX_REV_MINOR 0x00
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/* Shared Values */
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#define BUS_SPEED_100KHz 100000 /* 100 KHz */
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#define BUS_SPEED_400KHz 400000 /* 400 KHz */
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#define I2C_OWN_ADDRESS 0x01
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/* Masks */
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#define ADDRESS_MASK (0x3ff) /* Highest 10 bit address -- 9..0 */
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/* Bit Offsets within Registers (only those used are listed) */
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/* Same offsets for both dm37xx and am335x */
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#define I2C_EN 15 /* I2C_CON */
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#define MST 10 /* I2C_CON */
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#define TRX 9 /* I2C_CON */
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#define XSA 8 /* I2C_CON */
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#define STP 1 /* I2C_CON */
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#define STT 0 /* I2C_CON */
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#define CLKACTIVITY_S 9 /* I2C_SYSC */
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#define CLKACTIVITY_I 8 /* I2C_SYSC */
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#define SMART_WAKE_UP 4 /* I2C_SYSC */
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#define NO_IDLE_MODE 3 /* I2C_SYSC */
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#define SRST 1 /* I2C_SYSC */
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#define AUTOIDLE 0 /* I2C_SYSC */
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#define RDONE 0 /* I2C_SYSS */
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#define RXFIFO_CLR 14 /* I2C_BUF */
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#define TXFIFO_CLR 6 /* I2C_BUF */
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#define BB 12 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#define ROVR 11 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#define AERR 7 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#define XRDY 4 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#define RRDY 3 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#define ARDY 2 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#define NACK 1 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#define AL 0 /* I2C_IRQSTATUS / I2C_STAT / I2C_IRQENABLE_SET / I2C_IE */
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#endif /* _OMAP_I2C_REGISTERS_H */
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