120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
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/* $NetBSD: strmacros.h,v 1.1 2013/03/17 00:42:32 christos Exp $ */
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/*
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* Copyright (c) 1996-2002 Eduardo Horvath
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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*notice, this list of conditions and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <machine/asm.h>
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#if defined(_KERNEL) && !defined(_RUMPKERNEL)
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#define USE_BLOCK_STORE_LOAD /* enable block load/store ops */
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#include "assym.h"
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#include <machine/param.h>
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#include <machine/ctlreg.h>
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#include <machine/psl.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <machine/locore.h>
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#ifdef USE_BLOCK_STORE_LOAD
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#define BLOCK_SIZE SPARC64_BLOCK_SIZE
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#define BLOCK_ALIGN SPARC64_BLOCK_ALIGN
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/*
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* The following routines allow fpu use in the kernel.
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*
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* They allocate a stack frame and use all local regs. Extra
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* local storage can be requested by setting the siz parameter,
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* and can be accessed at %sp+CC64FSZ.
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*/
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#define ENABLE_FPU(siz) \
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save %sp, -(CC64FSZ), %sp; /* Allocate a stack frame */ \
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sethi %hi(FPLWP), %l1; \
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add %fp, STKB-FS_SIZE, %l0; /* Allocate a fpstate */\
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LDPTR [%l1 + %lo(FPLWP)], %l2; /* Load fplwp */ \
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andn %l0, BLOCK_ALIGN, %l0; /* Align it */ \
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clr %l3; /* NULL fpstate */ \
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brz,pt %l2, 1f; /* fplwp == NULL? */ \
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add %l0, -STKB-CC64FSZ-(siz), %sp; /* Set proper %sp */ \
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LDPTR [%l2 + L_FPSTATE], %l3; \
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brz,pn %l3, 1f; /* Make sure we have an fpstate */ \
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mov %l3, %o0; \
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call _C_LABEL(savefpstate); /* Save the old fpstate */ \
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1: \
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set EINTSTACK-STKB, %l4; /* Are we on intr stack? */ \
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cmp %sp, %l4; \
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bgu,pt %xcc, 1f; \
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set INTSTACK-STKB, %l4; \
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cmp %sp, %l4; \
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blu %xcc, 1f; \
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0: \
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sethi %hi(_C_LABEL(lwp0)), %l4; /* Yes, use lpw0 */ \
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ba,pt %xcc, 2f; /* XXXX needs to change to CPUs idle proc */ \
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or %l4, %lo(_C_LABEL(lwp0)), %l5; \
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1: \
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sethi %hi(CURLWP), %l4; /* Use curlwp */ \
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LDPTR [%l4 + %lo(CURLWP)], %l5; \
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brz,pn %l5, 0b; nop; /* If curlwp is NULL need to use lwp0 */\
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2: \
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LDPTR [%l5 + L_FPSTATE], %l6; /* Save old fpstate */ \
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STPTR %l0, [%l5 + L_FPSTATE]; /* Insert new fpstate */\
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STPTR %l5, [%l1 + %lo(FPLWP)]; /* Set new fplwp */ \
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wr %g0, FPRS_FEF, %fprs /* Enable FPU */
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/*
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* Weve saved our possible fpstate, now disable the fpu
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* and continue with life.
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*/
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#ifdef DEBUG
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#define __CHECK_FPU \
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LDPTR [%l5 + L_FPSTATE], %l7; \
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cmp %l7, %l0; \
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tnz 1;
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#else
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#define __CHECK_FPU
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#endif
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#define RESTORE_FPU \
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__CHECK_FPU \
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STPTR %l2, [%l1 + %lo(FPLWP)]; /* Restore old fproc */ \
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wr %g0, 0, %fprs; /* Disable fpu */ \
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brz,pt %l3, 1f; /* Skip if no fpstate */ \
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STPTR %l6, [%l5 + L_FPSTATE]; /* Restore old fpstate */\
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\
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mov %l3, %o0; \
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call _C_LABEL(loadfpstate); /* Reload orig fpstate */\
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1: \
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membar #Sync; /* Finish all FP ops */
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#endif /* USE_BLOCK_STORE_LOAD */
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#ifdef USE_BLOCK_STORE_LOAD
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#if 0
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#define ASI_STORE ASI_BLK_COMMIT_P
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#else
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#define ASI_STORE ASI_BLK_P
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#endif
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#endif /* USE_BLOCK_STORE_LOAD */
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#endif /* _KERNEL && !_RUMPKERNEL */
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