203 lines
7.3 KiB
C
203 lines
7.3 KiB
C
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/* $NetBSD: sdhcreg.h,v 1.6 2012/03/02 18:20:34 nonaka Exp $ */
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/* $OpenBSD: sdhcreg.h,v 1.4 2006/07/30 17:20:40 fgsch Exp $ */
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _SDHCREG_H_
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#define _SDHCREG_H_
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/* Host standard register set */
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#define SDHC_DMA_ADDR 0x00
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#define SDHC_BLOCK_SIZE 0x04
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#define SDHC_BLOCK_COUNT 0x06
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#define SDHC_BLOCK_COUNT_MAX 512
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#define SDHC_ARGUMENT 0x08
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#define SDHC_TRANSFER_MODE 0x0c
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#define SDHC_MULTI_BLOCK_MODE (1<<5)
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#define SDHC_READ_MODE (1<<4)
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#define SDHC_AUTO_CMD12_ENABLE (1<<2)
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#define SDHC_BLOCK_COUNT_ENABLE (1<<1)
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#define SDHC_DMA_ENABLE (1<<0)
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#define SDHC_COMMAND 0x0e
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/* 14-15 reserved */
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#define SDHC_COMMAND_INDEX_SHIFT 8
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#define SDHC_COMMAND_INDEX_MASK 0x3f
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#define SDHC_COMMAND_TYPE_ABORT (3<<6)
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#define SDHC_COMMAND_TYPE_RESUME (2<<6)
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#define SDHC_COMMAND_TYPE_SUSPEND (1<<6)
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#define SDHC_COMMAND_TYPE_NORMAL (0<<6)
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#define SDHC_DATA_PRESENT_SELECT (1<<5)
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#define SDHC_INDEX_CHECK_ENABLE (1<<4)
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#define SDHC_CRC_CHECK_ENABLE (1<<3)
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/* 2 reserved */
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#define SDHC_RESP_LEN_48_CHK_BUSY (3<<0)
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#define SDHC_RESP_LEN_48 (2<<0)
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#define SDHC_RESP_LEN_136 (1<<0)
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#define SDHC_NO_RESPONSE (0<<0)
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#define SDHC_RESPONSE 0x10 /* - 0x1f */
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#define SDHC_DATA 0x20
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#define SDHC_PRESENT_STATE 0x24
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/* 25-31 reserved */
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#define SDHC_CMD_LINE_SIGNAL_LEVEL (1<<24)
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#define SDHC_DAT3_LINE_LEVEL (1<<23)
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#define SDHC_DAT2_LINE_LEVEL (1<<22)
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#define SDHC_DAT1_LINE_LEVEL (1<<21)
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#define SDHC_DAT0_LINE_LEVEL (1<<20)
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#define SDHC_WRITE_PROTECT_SWITCH (1<<19)
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#define SDHC_CARD_DETECT_PIN_LEVEL (1<<18)
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#define SDHC_CARD_STATE_STABLE (1<<17)
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#define SDHC_CARD_INSERTED (1<<16)
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/* 12-15 reserved */
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#define SDHC_BUFFER_READ_ENABLE (1<<11)
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#define SDHC_BUFFER_WRITE_ENABLE (1<<10)
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#define SDHC_READ_TRANSFER_ACTIVE (1<<9)
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#define SDHC_WRITE_TRANSFER_ACTIVE (1<<8)
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/* 3-7 reserved */
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#define SDHC_DAT_ACTIVE (1<<2)
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#define SDHC_CMD_INHIBIT_DAT (1<<1)
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#define SDHC_CMD_INHIBIT_CMD (1<<0)
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#define SDHC_CMD_INHIBIT_MASK 0x0003
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#define SDHC_HOST_CTL 0x28
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#define SDHC_HIGH_SPEED (1<<2)
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#define SDHC_ESDHC_8BIT_MODE (1<<2) /* eSDHC */
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#define SDHC_4BIT_MODE (1<<1)
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#define SDHC_LED_ON (1<<0)
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#define SDHC_POWER_CTL 0x29
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#define SDHC_VOLTAGE_SHIFT 1
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#define SDHC_VOLTAGE_MASK 0x07
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#define SDHC_VOLTAGE_3_3V 0x07
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#define SDHC_VOLTAGE_3_0V 0x06
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#define SDHC_VOLTAGE_1_8V 0x05
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#define SDHC_BUS_POWER (1<<0)
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#define SDHC_BLOCK_GAP_CTL 0x2a
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#define SDHC_WAKEUP_CTL 0x2b
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#define SDHC_CLOCK_CTL 0x2c
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#define SDHC_SDCLK_DIV_SHIFT 8
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#define SDHC_SDCLK_DIV_MASK 0xff
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#define SDHC_SDCLK_XDIV_SHIFT 6
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#define SDHC_SDCLK_XDIV_MASK 0x3
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#define SDHC_SDCLK_CGM (1<<5)
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#define SDHC_SDCLK_DVS_SHIFT 4
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#define SDHC_SDCLK_DVS_MASK 0xf
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#define SDHC_SDCLK_ENABLE (1<<2)
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#define SDHC_INTCLK_STABLE (1<<1)
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#define SDHC_INTCLK_ENABLE (1<<0)
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#define SDHC_TIMEOUT_CTL 0x2e
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#define SDHC_TIMEOUT_MAX 0x0e
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#define SDHC_SOFTWARE_RESET 0x2f
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#define SDHC_INIT_ACTIVE (1<<3)
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#define SDHC_RESET_MASK 0x5
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#define SDHC_RESET_DAT (1<<2)
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#define SDHC_RESET_CMD (1<<1)
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#define SDHC_RESET_ALL (1<<0)
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#define SDHC_NINTR_STATUS 0x30
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#define SDHC_ERROR_INTERRUPT (1<<15)
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#define SDHC_CARD_INTERRUPT (1<<8)
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#define SDHC_CARD_REMOVAL (1<<7)
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#define SDHC_CARD_INSERTION (1<<6)
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#define SDHC_BUFFER_READ_READY (1<<5)
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#define SDHC_BUFFER_WRITE_READY (1<<4)
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#define SDHC_DMA_INTERRUPT (1<<3)
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#define SDHC_BLOCK_GAP_EVENT (1<<2)
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#define SDHC_TRANSFER_COMPLETE (1<<1)
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#define SDHC_COMMAND_COMPLETE (1<<0)
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#define SDHC_NINTR_STATUS_MASK 0x81ff
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#define SDHC_EINTR_STATUS 0x32
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#define SDHC_DMA_ERROR (1<<12)
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#define SDHC_AUTO_CMD12_ERROR (1<<8)
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#define SDHC_CURRENT_LIMIT_ERROR (1<<7)
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#define SDHC_DATA_END_BIT_ERROR (1<<6)
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#define SDHC_DATA_CRC_ERROR (1<<5)
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#define SDHC_DATA_TIMEOUT_ERROR (1<<4)
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#define SDHC_CMD_INDEX_ERROR (1<<3)
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#define SDHC_CMD_END_BIT_ERROR (1<<2)
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#define SDHC_CMD_CRC_ERROR (1<<1)
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#define SDHC_CMD_TIMEOUT_ERROR (1<<0)
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#define SDHC_EINTR_STATUS_MASK 0x01ff /* excluding vendor signals */
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#define SDHC_NINTR_STATUS_EN 0x34
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#define SDHC_EINTR_STATUS_EN 0x36
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#define SDHC_NINTR_SIGNAL_EN 0x38
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#define SDHC_NINTR_SIGNAL_MASK 0x01ff
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#define SDHC_EINTR_SIGNAL_EN 0x3a
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#define SDHC_EINTR_SIGNAL_MASK 0x01ff /* excluding vendor signals */
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#define SDHC_CMD12_ERROR_STATUS 0x3c
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#define SDHC_CAPABILITIES 0x40
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#define SDHC_VOLTAGE_SUPP_1_8V (1<<26)
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#define SDHC_VOLTAGE_SUPP_3_0V (1<<25)
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#define SDHC_VOLTAGE_SUPP_3_3V (1<<24)
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#define SDHC_DMA_SUPPORT (1<<22)
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#define SDHC_HIGH_SPEED_SUPP (1<<21)
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#define SDHC_MAX_BLK_LEN_512 0
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#define SDHC_MAX_BLK_LEN_1024 1
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#define SDHC_MAX_BLK_LEN_2048 2
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#define SDHC_MAX_BLK_LEN_4096 3
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#define SDHC_MAX_BLK_LEN_SHIFT 16
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#define SDHC_MAX_BLK_LEN_MASK 0x3
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#define SDHC_BASE_FREQ_SHIFT 8
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#define SDHC_BASE_FREQ_MASK 0x3f
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#define SDHC_TIMEOUT_FREQ_UNIT (1<<7) /* 0=KHz, 1=MHz */
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#define SDHC_TIMEOUT_FREQ_SHIFT 0
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#define SDHC_TIMEOUT_FREQ_MASK 0x1f
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#define SDHC_MAX_CAPABILITIES 0x48
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#define SDHC_HOST_VER 0xFC
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#define SDHC_VVN_MASK 0x0f
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#define SDHC_VVN_SHIFT 0x04
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#define SDHC_SVN_MASK 0x0f
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#define SDHC_SVN_SHIFT 0x00
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#define SDHC_SLOT_INTR_STATUS 0xfc
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#define SDHC_HOST_CTL_VERSION 0xfe
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#define SDHC_SPEC_VERS_SHIFT 0
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#define SDHC_SPEC_VERS_MASK 0xff
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#define SDHC_VENDOR_VERS_SHIFT 8
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#define SDHC_VENDOR_VERS_MASK 0xff
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#define SDHC_DMA_CTL 0x40c /* eSDHC */
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#define SDHC_DMA_SNOOP 0x40
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/* SDHC_SPEC_VERS */
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#define SDHC_SPEC_VERS_100 0x00
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#define SDHC_SPEC_VERS_200 0x01
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#define SDHC_SPEC_VERS_300 0x02
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/* SDHC_CAPABILITIES decoding */
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#define SDHC_BASE_FREQ_KHZ(cap) \
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((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000)
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#define SDHC_TIMEOUT_FREQ(cap) \
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(((cap) >> SDHC_TIMEOUT_FREQ_SHIFT) & SDHC_TIMEOUT_FREQ_MASK)
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#define SDHC_TIMEOUT_FREQ_KHZ(cap) \
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(((cap) & SDHC_TIMEOUT_FREQ_UNIT) ? \
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SDHC_TIMEOUT_FREQ(cap) * 1000: \
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SDHC_TIMEOUT_FREQ(cap))
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/* SDHC_HOST_CTL_VERSION decoding */
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#define SDHC_SPEC_VERSION(hcv) \
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(((hcv) >> SDHC_SPEC_VERS_SHIFT) & SDHC_SPEC_VERS_MASK)
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#define SDHC_VENDOR_VERSION(hcv) \
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(((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK)
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#define SDHC_PRESENT_STATE_BITS \
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"\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" \
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"\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC"
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#define SDHC_NINTR_STATUS_BITS \
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"\20\20ERROR\11CARD\10REMOVAL\7INSERTION\6READ\5WRITE" \
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"\4DMA\3GAP\2XFER\1CMD"
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#define SDHC_EINTR_STATUS_BITS \
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"\20\11ACMD12\10CL\7DEB\6DCRC\5DT\4CI\3CEB\2CCRC\1CT"
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#define SDHC_CAPABILITIES_BITS \
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"\20\33Vdd1.8V\32Vdd3.0V\31Vdd3.3V\30SUSPEND\27DMA\26HIGHSPEED"
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#endif /* _SDHCREG_H_ */
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