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minix/kernel/arch/i386/apic_asm.S

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ArmAsm
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Move archtypes.h, fpu.h, and stackframe.h Move archtypes.h to include/ dir, since several servers require it. Move fpu.h and stackframe.h to arch-specific header directory. Make source files and makefiles aware of the new header locations.
2010-03-09 10:41:14 +01:00
#include "archconst.h"
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
#include "apic.h"
#include "sconst.h"
#include "apic_asm.h"
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
#include <machine/asm.h>
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
#define APIC_IRQ_HANDLER(irq) \
APIC mode uses IO APICs - kernel turns on IO APICs if no_apic is _not_ set or is equal 0 - pci driver must use the acpi driver to setup IRQ routing otherwise the system cannot work correctly except systems like KVM that use only legacy (E)ISA IRQs 0-15
2010-09-07 09:18:11 +02:00
push $irq ;\
call _C_LABEL(irq_handle) /* intr_handle(irq) */ ;\
add $4, %esp ;
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
/*===========================================================================*/
/* interrupt handlers */
/* interrupt handlers for 386 32-bit protected mode */
/* APIC interrupt handlers for 386 32-bit protected mode */
/*===========================================================================*/
APIC mode uses IO APICs - kernel turns on IO APICs if no_apic is _not_ set or is equal 0 - pci driver must use the acpi driver to setup IRQ routing otherwise the system cannot work correctly except systems like KVM that use only legacy (E)ISA IRQs 0-15
2010-09-07 09:18:11 +02:00
#define apic_hwint(irq) \
ENTRY(apic_hwint##irq) \
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
TEST_INT_IN_KERNEL(4, 0f) ;\
\
SAVE_PROCESS_CTX(0) ;\
Time accounting based on TSC - as thre are still KERNEL and IDLE entries, time accounting for kernel and idle time works the same as for any other process - everytime we stop accounting for the currently running process, kernel or idle, we read the TSC counter and increment the p_cycles entry. - the process cycles inherently include some of the kernel cycles as we can stop accounting for the process only after we save its context and we start accounting just before we restore its context - this assumes that the system does not scale the CPU frequency which will be true for ... long time ;-)
2010-02-10 16:36:54 +01:00
push %ebp ;\
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
call _C_LABEL(context_stop) ;\
Time accounting based on TSC - as thre are still KERNEL and IDLE entries, time accounting for kernel and idle time works the same as for any other process - everytime we stop accounting for the currently running process, kernel or idle, we read the TSC counter and increment the p_cycles entry. - the process cycles inherently include some of the kernel cycles as we can stop accounting for the process only after we save its context and we start accounting just before we restore its context - this assumes that the system does not scale the CPU frequency which will be true for ... long time ;-)
2010-02-10 16:36:54 +01:00
add $4, %esp ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
movl $0, %ebp /* for stack trace */ ;\
APIC_IRQ_HANDLER(irq) ;\
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
jmp _C_LABEL(switch_to_user) ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
\
0: \
pusha ;\
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
call _C_LABEL(context_stop_idle) ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
APIC_IRQ_HANDLER(irq) ;\
Interrupts hadling while idle - When the cpu halts, the interrupts are enable so the cpu may be woken up. When the interrupt handler returns but another interrupt is available it is also serviced immediately. This is not a problem per-se. It only slightly breaks time accounting as idle accounted is for the kernel time in the interrupt handler. - As the big kernel lock is lock/unlocked in the smp branch in the time acounting functions as they are called exactly at the places we need to take the lock) this leads to a deadlock. - we make sure that once the interrupt handler returns from the nested trap, the interrupts are disabled. This means that only one interrupt is serviced after idle is interrupted. - this requires the loop in apic timer calibration to keep reenabling the interrupts. I admit it is a little bit hackish (one line), however, this code is a stupid corner case at the boot time. Hopefully it does not matter too much.
2010-03-23 14:35:01 +01:00
CLEAR_IF(10*4(%esp)) ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
popa ;\
iret ;
#define LAPIC_INTR_HANDLER(func) \
movl $func, %eax ;\
call *%eax /* call the actual handler */ ;\
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
mov _C_LABEL(lapic_eoi_addr), %eax /* the end of handler*/ ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
movl $0, (%eax) ;
/*===========================================================================*/
/* handler of the local APIC interrupts */
/*===========================================================================*/
#define lapic_intr(func) \
TEST_INT_IN_KERNEL(4, 0f) ;\
\
SAVE_PROCESS_CTX(0) ;\
Time accounting based on TSC - as thre are still KERNEL and IDLE entries, time accounting for kernel and idle time works the same as for any other process - everytime we stop accounting for the currently running process, kernel or idle, we read the TSC counter and increment the p_cycles entry. - the process cycles inherently include some of the kernel cycles as we can stop accounting for the process only after we save its context and we start accounting just before we restore its context - this assumes that the system does not scale the CPU frequency which will be true for ... long time ;-)
2010-02-10 16:36:54 +01:00
push %ebp ;\
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
call _C_LABEL(context_stop) ;\
Time accounting based on TSC - as thre are still KERNEL and IDLE entries, time accounting for kernel and idle time works the same as for any other process - everytime we stop accounting for the currently running process, kernel or idle, we read the TSC counter and increment the p_cycles entry. - the process cycles inherently include some of the kernel cycles as we can stop accounting for the process only after we save its context and we start accounting just before we restore its context - this assumes that the system does not scale the CPU frequency which will be true for ... long time ;-)
2010-02-10 16:36:54 +01:00
add $4, %esp ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
movl $0, %ebp /* for stack trace */ ;\
LAPIC_INTR_HANDLER(func) ;\
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
jmp _C_LABEL(switch_to_user) ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
\
0: \
pusha ;\
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
call _C_LABEL(context_stop_idle) ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
LAPIC_INTR_HANDLER(func) ;\
Interrupts hadling while idle - When the cpu halts, the interrupts are enable so the cpu may be woken up. When the interrupt handler returns but another interrupt is available it is also serviced immediately. This is not a problem per-se. It only slightly breaks time accounting as idle accounted is for the kernel time in the interrupt handler. - As the big kernel lock is lock/unlocked in the smp branch in the time acounting functions as they are called exactly at the places we need to take the lock) this leads to a deadlock. - we make sure that once the interrupt handler returns from the nested trap, the interrupts are disabled. This means that only one interrupt is serviced after idle is interrupted. - this requires the loop in apic timer calibration to keep reenabling the interrupts. I admit it is a little bit hackish (one line), however, this code is a stupid corner case at the boot time. Hopefully it does not matter too much.
2010-03-23 14:35:01 +01:00
CLEAR_IF(10*4(%esp)) ;\
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
popa ;\
iret ;
/* apic timer tick handlers */
SMP - Only a single APIC timer handler - bsp_timer_int_handler() and ap_timer_int_handler() unified into timer_int_handler() - global realtime updated only on BSP
2010-09-15 16:10:09 +02:00
ENTRY(lapic_timer_int_handler)
lapic_intr(_C_LABEL(timer_int_handler))
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
spurious and error interrupt apic handlers - fixed spurious and error interrupt handlers - not to hog the system the warning isn't reported every time, just once every 100 times, similarly for the spurious PIC interrupts
2010-10-19 19:07:21 +02:00
ENTRY(apic_spurios_intr)
lapic_intr(_C_LABEL(apic_spurios_intr_handler))
ENTRY(apic_error_intr)
lapic_intr(_C_LABEL(apic_error_intr_handler))
SMP - We boot APs - kernel detects CPUs by searching ACPI tables for local apic nodes - each CPU has its own TSS that points to its own stack. All cpus boot on the same boot stack (in sequence) but switch to its private stack as soon as they can. - final booting code in main() placed in bsp_finish_booting() which is executed only after the BSP switches to its final stack - apic functions to send startup interrupts - assembler functions to handle CPU features not needed for single cpu mode like memory barries, HT detection etc. - new files kernel/smp.[ch], kernel/arch/i386/arch_smp.c and kernel/arch/i386/include/arch_smp.h - 16-bit trampoline code for the APs. It is executed by each AP after receiving startup IPIs it brings up the CPUs to 32bit mode and let them spin in an infinite loop so they don't do any damage. - implementation of kernel spinlock - CONFIG_SMP and CONFIG_MAX_CPUS set by the build system
2010-09-15 16:09:52 +02:00
#ifdef CONFIG_SMP
SMP - APs are fully enabled - apic_send_ipi() to send inter-processor interrupts (IPIs) - APIC IPI schedule and halt handlers to signal x-cpu that a cpu shold reschedule or halt - various little changes to let APs run - no processes are scheduled at the APs and therefore they are idle except being interrupted by a timer time to time
2010-09-15 16:10:30 +02:00
ENTRY(apic_ipi_sched_intr)
SMP - trully idle APs - any cpu can use smp_schedule() to tell another cpu to reschedule - if an AP is idle, it turns off timer as there is nothing to preempt, no need to wakeup just to go back to sleep again - if a cpu makes a process runnable on an idle cpu, it must wake it up to reschedule
2010-09-15 16:10:57 +02:00
lapic_intr(_C_LABEL(smp_ipi_sched_handler))
SMP - We boot APs - kernel detects CPUs by searching ACPI tables for local apic nodes - each CPU has its own TSS that points to its own stack. All cpus boot on the same boot stack (in sequence) but switch to its private stack as soon as they can. - final booting code in main() placed in bsp_finish_booting() which is executed only after the BSP switches to its final stack - apic functions to send startup interrupts - assembler functions to handle CPU features not needed for single cpu mode like memory barries, HT detection etc. - new files kernel/smp.[ch], kernel/arch/i386/arch_smp.c and kernel/arch/i386/include/arch_smp.h - 16-bit trampoline code for the APs. It is executed by each AP after receiving startup IPIs it brings up the CPUs to 32bit mode and let them spin in an infinite loop so they don't do any damage. - implementation of kernel spinlock - CONFIG_SMP and CONFIG_MAX_CPUS set by the build system
2010-09-15 16:09:52 +02:00
SMP - APs are fully enabled - apic_send_ipi() to send inter-processor interrupts (IPIs) - APIC IPI schedule and halt handlers to signal x-cpu that a cpu shold reschedule or halt - various little changes to let APs run - no processes are scheduled at the APs and therefore they are idle except being interrupted by a timer time to time
2010-09-15 16:10:30 +02:00
ENTRY(apic_ipi_halt_intr)
SMP - BSP halts APs before shutting down
2010-09-15 16:10:54 +02:00
lapic_intr(_C_LABEL(smp_ipi_halt_handler))
SMP - We boot APs - kernel detects CPUs by searching ACPI tables for local apic nodes - each CPU has its own TSS that points to its own stack. All cpus boot on the same boot stack (in sequence) but switch to its private stack as soon as they can. - final booting code in main() placed in bsp_finish_booting() which is executed only after the BSP switches to its final stack - apic functions to send startup interrupts - assembler functions to handle CPU features not needed for single cpu mode like memory barries, HT detection etc. - new files kernel/smp.[ch], kernel/arch/i386/arch_smp.c and kernel/arch/i386/include/arch_smp.h - 16-bit trampoline code for the APs. It is executed by each AP after receiving startup IPIs it brings up the CPUs to 32bit mode and let them spin in an infinite loop so they don't do any damage. - implementation of kernel spinlock - CONFIG_SMP and CONFIG_MAX_CPUS set by the build system
2010-09-15 16:09:52 +02:00
#endif /* CONFIG_SMP */
Add MKAPIC and MKACPI options
2011-07-31 16:20:34 +02:00
#ifdef APIC_DEBUG
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
.data
lapic_intr_dummy_handler_msg:
APIC mode uses IO APICs - kernel turns on IO APICs if no_apic is _not_ set or is equal 0 - pci driver must use the acpi driver to setup IRQ routing otherwise the system cannot work correctly except systems like KVM that use only legacy (E)ISA IRQs 0-15
2010-09-07 09:18:11 +02:00
.ascii "UNHANDLED APIC interrupt vector %d\n"
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
.text
#define lapic_intr_dummy_handler(vect) \
pushl $vect; \
push $lapic_intr_dummy_handler_msg; \
panic in dummy apic handlers - as panic can do the same as printf now, let's rather panic when a dummy apic interrupt vector handler is hit
2010-10-19 19:07:17 +02:00
call _C_LABEL(panic); \
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
1: jmp 1b; /* never return */
#define LAPIC_INTR_DUMMY_HANDLER(vect) \
.balign LAPIC_INTR_DUMMY_HANDLER_SIZE; \
SMP - We boot APs - kernel detects CPUs by searching ACPI tables for local apic nodes - each CPU has its own TSS that points to its own stack. All cpus boot on the same boot stack (in sequence) but switch to its private stack as soon as they can. - final booting code in main() placed in bsp_finish_booting() which is executed only after the BSP switches to its final stack - apic functions to send startup interrupts - assembler functions to handle CPU features not needed for single cpu mode like memory barries, HT detection etc. - new files kernel/smp.[ch], kernel/arch/i386/arch_smp.c and kernel/arch/i386/include/arch_smp.h - 16-bit trampoline code for the APs. It is executed by each AP after receiving startup IPIs it brings up the CPUs to 32bit mode and let them spin in an infinite loop so they don't do any damage. - implementation of kernel spinlock - CONFIG_SMP and CONFIG_MAX_CPUS set by the build system
2010-09-15 16:09:52 +02:00
_lapic_intr_dummy_handler_##vect: lapic_intr_dummy_handler(vect)
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
APIC mode uses IO APICs - kernel turns on IO APICs if no_apic is _not_ set or is equal 0 - pci driver must use the acpi driver to setup IRQ routing otherwise the system cannot work correctly except systems like KVM that use only legacy (E)ISA IRQs 0-15
2010-09-07 09:18:11 +02:00
apic_hwint(0)
apic_hwint(1)
apic_hwint(2)
apic_hwint(3)
apic_hwint(4)
apic_hwint(5)
apic_hwint(6)
apic_hwint(7)
apic_hwint(8)
apic_hwint(9)
apic_hwint(10)
apic_hwint(11)
apic_hwint(12)
apic_hwint(13)
apic_hwint(14)
apic_hwint(15)
apic_hwint(16)
apic_hwint(17)
apic_hwint(18)
apic_hwint(19)
apic_hwint(20)
apic_hwint(21)
apic_hwint(22)
apic_hwint(23)
apic_hwint(24)
apic_hwint(25)
apic_hwint(26)
apic_hwint(27)
apic_hwint(28)
apic_hwint(29)
apic_hwint(30)
apic_hwint(31)
apic_hwint(32)
apic_hwint(33)
apic_hwint(34)
apic_hwint(35)
apic_hwint(36)
apic_hwint(37)
apic_hwint(38)
apic_hwint(39)
apic_hwint(40)
apic_hwint(41)
apic_hwint(42)
apic_hwint(43)
apic_hwint(44)
apic_hwint(45)
apic_hwint(46)
apic_hwint(47)
apic_hwint(48)
apic_hwint(49)
apic_hwint(50)
apic_hwint(51)
apic_hwint(52)
apic_hwint(53)
apic_hwint(54)
apic_hwint(55)
apic_hwint(56)
apic_hwint(57)
apic_hwint(58)
apic_hwint(59)
apic_hwint(60)
apic_hwint(61)
apic_hwint(62)
apic_hwint(63)
Macros for symbols used in both ASM and C -The macros take care of prepending the leading underscore when necessary.
2010-08-17 18:44:07 +02:00
LABEL(lapic_intr_dummy_handles_start)
LAPIC_INTR_DUMMY_HANDLER(0)
LAPIC_INTR_DUMMY_HANDLER(1)
LAPIC_INTR_DUMMY_HANDLER(2)
LAPIC_INTR_DUMMY_HANDLER(3)
LAPIC_INTR_DUMMY_HANDLER(4)
LAPIC_INTR_DUMMY_HANDLER(5)
LAPIC_INTR_DUMMY_HANDLER(6)
LAPIC_INTR_DUMMY_HANDLER(7)
LAPIC_INTR_DUMMY_HANDLER(8)
LAPIC_INTR_DUMMY_HANDLER(9)
LAPIC_INTR_DUMMY_HANDLER(10)
LAPIC_INTR_DUMMY_HANDLER(11)
LAPIC_INTR_DUMMY_HANDLER(12)
LAPIC_INTR_DUMMY_HANDLER(13)
LAPIC_INTR_DUMMY_HANDLER(14)
LAPIC_INTR_DUMMY_HANDLER(15)
LAPIC_INTR_DUMMY_HANDLER(16)
LAPIC_INTR_DUMMY_HANDLER(17)
LAPIC_INTR_DUMMY_HANDLER(18)
LAPIC_INTR_DUMMY_HANDLER(19)
LAPIC_INTR_DUMMY_HANDLER(20)
LAPIC_INTR_DUMMY_HANDLER(21)
LAPIC_INTR_DUMMY_HANDLER(22)
LAPIC_INTR_DUMMY_HANDLER(23)
LAPIC_INTR_DUMMY_HANDLER(24)
LAPIC_INTR_DUMMY_HANDLER(25)
LAPIC_INTR_DUMMY_HANDLER(26)
LAPIC_INTR_DUMMY_HANDLER(27)
LAPIC_INTR_DUMMY_HANDLER(28)
LAPIC_INTR_DUMMY_HANDLER(29)
LAPIC_INTR_DUMMY_HANDLER(30)
LAPIC_INTR_DUMMY_HANDLER(31)
LAPIC_INTR_DUMMY_HANDLER(32)
LAPIC_INTR_DUMMY_HANDLER(33)
LAPIC_INTR_DUMMY_HANDLER(34)
LAPIC_INTR_DUMMY_HANDLER(35)
LAPIC_INTR_DUMMY_HANDLER(36)
LAPIC_INTR_DUMMY_HANDLER(37)
LAPIC_INTR_DUMMY_HANDLER(38)
LAPIC_INTR_DUMMY_HANDLER(39)
LAPIC_INTR_DUMMY_HANDLER(40)
LAPIC_INTR_DUMMY_HANDLER(41)
LAPIC_INTR_DUMMY_HANDLER(42)
LAPIC_INTR_DUMMY_HANDLER(43)
LAPIC_INTR_DUMMY_HANDLER(44)
LAPIC_INTR_DUMMY_HANDLER(45)
LAPIC_INTR_DUMMY_HANDLER(46)
LAPIC_INTR_DUMMY_HANDLER(47)
LAPIC_INTR_DUMMY_HANDLER(48)
LAPIC_INTR_DUMMY_HANDLER(49)
LAPIC_INTR_DUMMY_HANDLER(50)
LAPIC_INTR_DUMMY_HANDLER(51)
LAPIC_INTR_DUMMY_HANDLER(52)
LAPIC_INTR_DUMMY_HANDLER(53)
LAPIC_INTR_DUMMY_HANDLER(54)
LAPIC_INTR_DUMMY_HANDLER(55)
LAPIC_INTR_DUMMY_HANDLER(56)
LAPIC_INTR_DUMMY_HANDLER(57)
LAPIC_INTR_DUMMY_HANDLER(58)
LAPIC_INTR_DUMMY_HANDLER(59)
LAPIC_INTR_DUMMY_HANDLER(60)
LAPIC_INTR_DUMMY_HANDLER(61)
LAPIC_INTR_DUMMY_HANDLER(62)
LAPIC_INTR_DUMMY_HANDLER(63)
LAPIC_INTR_DUMMY_HANDLER(64)
LAPIC_INTR_DUMMY_HANDLER(65)
LAPIC_INTR_DUMMY_HANDLER(66)
LAPIC_INTR_DUMMY_HANDLER(67)
LAPIC_INTR_DUMMY_HANDLER(68)
LAPIC_INTR_DUMMY_HANDLER(69)
LAPIC_INTR_DUMMY_HANDLER(70)
LAPIC_INTR_DUMMY_HANDLER(71)
LAPIC_INTR_DUMMY_HANDLER(72)
LAPIC_INTR_DUMMY_HANDLER(73)
LAPIC_INTR_DUMMY_HANDLER(74)
LAPIC_INTR_DUMMY_HANDLER(75)
LAPIC_INTR_DUMMY_HANDLER(76)
LAPIC_INTR_DUMMY_HANDLER(77)
LAPIC_INTR_DUMMY_HANDLER(78)
LAPIC_INTR_DUMMY_HANDLER(79)
LAPIC_INTR_DUMMY_HANDLER(80)
LAPIC_INTR_DUMMY_HANDLER(81)
LAPIC_INTR_DUMMY_HANDLER(82)
LAPIC_INTR_DUMMY_HANDLER(83)
LAPIC_INTR_DUMMY_HANDLER(84)
LAPIC_INTR_DUMMY_HANDLER(85)
LAPIC_INTR_DUMMY_HANDLER(86)
LAPIC_INTR_DUMMY_HANDLER(87)
LAPIC_INTR_DUMMY_HANDLER(88)
LAPIC_INTR_DUMMY_HANDLER(89)
LAPIC_INTR_DUMMY_HANDLER(90)
LAPIC_INTR_DUMMY_HANDLER(91)
LAPIC_INTR_DUMMY_HANDLER(92)
LAPIC_INTR_DUMMY_HANDLER(93)
LAPIC_INTR_DUMMY_HANDLER(94)
LAPIC_INTR_DUMMY_HANDLER(95)
LAPIC_INTR_DUMMY_HANDLER(96)
LAPIC_INTR_DUMMY_HANDLER(97)
LAPIC_INTR_DUMMY_HANDLER(98)
LAPIC_INTR_DUMMY_HANDLER(99)
LAPIC_INTR_DUMMY_HANDLER(100)
LAPIC_INTR_DUMMY_HANDLER(101)
LAPIC_INTR_DUMMY_HANDLER(102)
LAPIC_INTR_DUMMY_HANDLER(103)
LAPIC_INTR_DUMMY_HANDLER(104)
LAPIC_INTR_DUMMY_HANDLER(105)
LAPIC_INTR_DUMMY_HANDLER(106)
LAPIC_INTR_DUMMY_HANDLER(107)
LAPIC_INTR_DUMMY_HANDLER(108)
LAPIC_INTR_DUMMY_HANDLER(109)
LAPIC_INTR_DUMMY_HANDLER(110)
LAPIC_INTR_DUMMY_HANDLER(111)
LAPIC_INTR_DUMMY_HANDLER(112)
LAPIC_INTR_DUMMY_HANDLER(113)
LAPIC_INTR_DUMMY_HANDLER(114)
LAPIC_INTR_DUMMY_HANDLER(115)
LAPIC_INTR_DUMMY_HANDLER(116)
LAPIC_INTR_DUMMY_HANDLER(117)
LAPIC_INTR_DUMMY_HANDLER(118)
LAPIC_INTR_DUMMY_HANDLER(119)
LAPIC_INTR_DUMMY_HANDLER(120)
LAPIC_INTR_DUMMY_HANDLER(121)
LAPIC_INTR_DUMMY_HANDLER(122)
LAPIC_INTR_DUMMY_HANDLER(123)
LAPIC_INTR_DUMMY_HANDLER(124)
LAPIC_INTR_DUMMY_HANDLER(125)
LAPIC_INTR_DUMMY_HANDLER(126)
LAPIC_INTR_DUMMY_HANDLER(127)
LAPIC_INTR_DUMMY_HANDLER(128)
LAPIC_INTR_DUMMY_HANDLER(129)
LAPIC_INTR_DUMMY_HANDLER(130)
LAPIC_INTR_DUMMY_HANDLER(131)
LAPIC_INTR_DUMMY_HANDLER(132)
LAPIC_INTR_DUMMY_HANDLER(133)
LAPIC_INTR_DUMMY_HANDLER(134)
LAPIC_INTR_DUMMY_HANDLER(135)
LAPIC_INTR_DUMMY_HANDLER(136)
LAPIC_INTR_DUMMY_HANDLER(137)
LAPIC_INTR_DUMMY_HANDLER(138)
LAPIC_INTR_DUMMY_HANDLER(139)
LAPIC_INTR_DUMMY_HANDLER(140)
LAPIC_INTR_DUMMY_HANDLER(141)
LAPIC_INTR_DUMMY_HANDLER(142)
LAPIC_INTR_DUMMY_HANDLER(143)
LAPIC_INTR_DUMMY_HANDLER(144)
LAPIC_INTR_DUMMY_HANDLER(145)
LAPIC_INTR_DUMMY_HANDLER(146)
LAPIC_INTR_DUMMY_HANDLER(147)
LAPIC_INTR_DUMMY_HANDLER(148)
LAPIC_INTR_DUMMY_HANDLER(149)
LAPIC_INTR_DUMMY_HANDLER(150)
LAPIC_INTR_DUMMY_HANDLER(151)
LAPIC_INTR_DUMMY_HANDLER(152)
LAPIC_INTR_DUMMY_HANDLER(153)
LAPIC_INTR_DUMMY_HANDLER(154)
LAPIC_INTR_DUMMY_HANDLER(155)
LAPIC_INTR_DUMMY_HANDLER(156)
LAPIC_INTR_DUMMY_HANDLER(157)
LAPIC_INTR_DUMMY_HANDLER(158)
LAPIC_INTR_DUMMY_HANDLER(159)
LAPIC_INTR_DUMMY_HANDLER(160)
LAPIC_INTR_DUMMY_HANDLER(161)
LAPIC_INTR_DUMMY_HANDLER(162)
LAPIC_INTR_DUMMY_HANDLER(163)
LAPIC_INTR_DUMMY_HANDLER(164)
LAPIC_INTR_DUMMY_HANDLER(165)
LAPIC_INTR_DUMMY_HANDLER(166)
LAPIC_INTR_DUMMY_HANDLER(167)
LAPIC_INTR_DUMMY_HANDLER(168)
LAPIC_INTR_DUMMY_HANDLER(169)
LAPIC_INTR_DUMMY_HANDLER(170)
LAPIC_INTR_DUMMY_HANDLER(171)
LAPIC_INTR_DUMMY_HANDLER(172)
LAPIC_INTR_DUMMY_HANDLER(173)
LAPIC_INTR_DUMMY_HANDLER(174)
LAPIC_INTR_DUMMY_HANDLER(175)
LAPIC_INTR_DUMMY_HANDLER(176)
LAPIC_INTR_DUMMY_HANDLER(177)
LAPIC_INTR_DUMMY_HANDLER(178)
LAPIC_INTR_DUMMY_HANDLER(179)
LAPIC_INTR_DUMMY_HANDLER(180)
LAPIC_INTR_DUMMY_HANDLER(181)
LAPIC_INTR_DUMMY_HANDLER(182)
LAPIC_INTR_DUMMY_HANDLER(183)
LAPIC_INTR_DUMMY_HANDLER(184)
LAPIC_INTR_DUMMY_HANDLER(185)
LAPIC_INTR_DUMMY_HANDLER(186)
LAPIC_INTR_DUMMY_HANDLER(187)
LAPIC_INTR_DUMMY_HANDLER(188)
LAPIC_INTR_DUMMY_HANDLER(189)
LAPIC_INTR_DUMMY_HANDLER(190)
LAPIC_INTR_DUMMY_HANDLER(191)
LAPIC_INTR_DUMMY_HANDLER(192)
LAPIC_INTR_DUMMY_HANDLER(193)
LAPIC_INTR_DUMMY_HANDLER(194)
LAPIC_INTR_DUMMY_HANDLER(195)
LAPIC_INTR_DUMMY_HANDLER(196)
LAPIC_INTR_DUMMY_HANDLER(197)
LAPIC_INTR_DUMMY_HANDLER(198)
LAPIC_INTR_DUMMY_HANDLER(199)
LAPIC_INTR_DUMMY_HANDLER(200)
LAPIC_INTR_DUMMY_HANDLER(201)
LAPIC_INTR_DUMMY_HANDLER(202)
LAPIC_INTR_DUMMY_HANDLER(203)
LAPIC_INTR_DUMMY_HANDLER(204)
LAPIC_INTR_DUMMY_HANDLER(205)
LAPIC_INTR_DUMMY_HANDLER(206)
LAPIC_INTR_DUMMY_HANDLER(207)
LAPIC_INTR_DUMMY_HANDLER(208)
LAPIC_INTR_DUMMY_HANDLER(209)
LAPIC_INTR_DUMMY_HANDLER(210)
LAPIC_INTR_DUMMY_HANDLER(211)
LAPIC_INTR_DUMMY_HANDLER(212)
LAPIC_INTR_DUMMY_HANDLER(213)
LAPIC_INTR_DUMMY_HANDLER(214)
LAPIC_INTR_DUMMY_HANDLER(215)
LAPIC_INTR_DUMMY_HANDLER(216)
LAPIC_INTR_DUMMY_HANDLER(217)
LAPIC_INTR_DUMMY_HANDLER(218)
LAPIC_INTR_DUMMY_HANDLER(219)
LAPIC_INTR_DUMMY_HANDLER(220)
LAPIC_INTR_DUMMY_HANDLER(221)
LAPIC_INTR_DUMMY_HANDLER(222)
LAPIC_INTR_DUMMY_HANDLER(223)
LAPIC_INTR_DUMMY_HANDLER(224)
LAPIC_INTR_DUMMY_HANDLER(225)
LAPIC_INTR_DUMMY_HANDLER(226)
LAPIC_INTR_DUMMY_HANDLER(227)
LAPIC_INTR_DUMMY_HANDLER(228)
LAPIC_INTR_DUMMY_HANDLER(229)
LAPIC_INTR_DUMMY_HANDLER(230)
LAPIC_INTR_DUMMY_HANDLER(231)
LAPIC_INTR_DUMMY_HANDLER(232)
LAPIC_INTR_DUMMY_HANDLER(233)
LAPIC_INTR_DUMMY_HANDLER(234)
LAPIC_INTR_DUMMY_HANDLER(235)
LAPIC_INTR_DUMMY_HANDLER(236)
LAPIC_INTR_DUMMY_HANDLER(237)
LAPIC_INTR_DUMMY_HANDLER(238)
LAPIC_INTR_DUMMY_HANDLER(239)
LAPIC_INTR_DUMMY_HANDLER(240)
LAPIC_INTR_DUMMY_HANDLER(241)
LAPIC_INTR_DUMMY_HANDLER(242)
LAPIC_INTR_DUMMY_HANDLER(243)
LAPIC_INTR_DUMMY_HANDLER(244)
LAPIC_INTR_DUMMY_HANDLER(245)
LAPIC_INTR_DUMMY_HANDLER(246)
LAPIC_INTR_DUMMY_HANDLER(247)
LAPIC_INTR_DUMMY_HANDLER(248)
LAPIC_INTR_DUMMY_HANDLER(249)
LAPIC_INTR_DUMMY_HANDLER(250)
LAPIC_INTR_DUMMY_HANDLER(251)
LAPIC_INTR_DUMMY_HANDLER(252)
LAPIC_INTR_DUMMY_HANDLER(253)
LAPIC_INTR_DUMMY_HANDLER(254)
LAPIC_INTR_DUMMY_HANDLER(255)
LABEL(lapic_intr_dummy_handles_end)
Local APIC - local APIC timer used as the source of time - PIC is still used as the hw interrupt controller as we don't have enough info without ACPI or MPS to set up IO APICs - remapping of APIC when switching paging on, uses the new mechanism to tell VM what phys areas to map in kernel's virtual space - one more step to SMP based on code by Arun C.
2009-11-16 22:41:44 +01:00
Add MKAPIC and MKACPI options
2011-07-31 16:20:34 +02:00
#endif /* APIC_DEBUG */
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