2005-08-05 11:53:08 +02:00
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/*
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dp8390.h
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Created: before Dec 28, 1992 by Philip Homburg
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*/
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/* National Semiconductor DP8390 Network Interface Controller. */
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/* Page 0, for reading ------------- */
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#define DP_CR 0x0 /* Read side of Command Register */
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#define DP_CLDA0 0x1 /* Current Local Dma Address 0 */
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#define DP_CLDA1 0x2 /* Current Local Dma Address 1 */
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#define DP_BNRY 0x3 /* Boundary Pointer */
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#define DP_TSR 0x4 /* Transmit Status Register */
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#define DP_NCR 0x5 /* Number of Collisions Register */
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#define DP_FIFO 0x6 /* Fifo ?? */
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#define DP_ISR 0x7 /* Interrupt Status Register */
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#define DP_CRDA0 0x8 /* Current Remote Dma Address 0 */
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#define DP_CRDA1 0x9 /* Current Remote Dma Address 1 */
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#define DP_DUM1 0xA /* unused */
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#define DP_DUM2 0xB /* unused */
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#define DP_RSR 0xC /* Receive Status Register */
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#define DP_CNTR0 0xD /* Tally Counter 0 */
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#define DP_CNTR1 0xE /* Tally Counter 1 */
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#define DP_CNTR2 0xF /* Tally Counter 2 */
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/* Page 0, for writing ------------- */
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#define DP_CR 0x0 /* Write side of Command Register */
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#define DP_PSTART 0x1 /* Page Start Register */
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#define DP_PSTOP 0x2 /* Page Stop Register */
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#define DP_BNRY 0x3 /* Boundary Pointer */
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#define DP_TPSR 0x4 /* Transmit Page Start Register */
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#define DP_TBCR0 0x5 /* Transmit Byte Count Register 0 */
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#define DP_TBCR1 0x6 /* Transmit Byte Count Register 1 */
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#define DP_ISR 0x7 /* Interrupt Status Register */
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#define DP_RSAR0 0x8 /* Remote Start Address Register 0 */
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#define DP_RSAR1 0x9 /* Remote Start Address Register 1 */
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#define DP_RBCR0 0xA /* Remote Byte Count Register 0 */
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#define DP_RBCR1 0xB /* Remote Byte Count Register 1 */
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#define DP_RCR 0xC /* Receive Configuration Register */
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#define DP_TCR 0xD /* Transmit Configuration Register */
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#define DP_DCR 0xE /* Data Configuration Register */
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#define DP_IMR 0xF /* Interrupt Mask Register */
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/* Page 1, read/write -------------- */
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#define DP_CR 0x0 /* Command Register */
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#define DP_PAR0 0x1 /* Physical Address Register 0 */
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#define DP_PAR1 0x2 /* Physical Address Register 1 */
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#define DP_PAR2 0x3 /* Physical Address Register 2 */
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#define DP_PAR3 0x4 /* Physical Address Register 3 */
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#define DP_PAR4 0x5 /* Physical Address Register 4 */
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#define DP_PAR5 0x6 /* Physical Address Register 5 */
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#define DP_CURR 0x7 /* Current Page Register */
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#define DP_MAR0 0x8 /* Multicast Address Register 0 */
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#define DP_MAR1 0x9 /* Multicast Address Register 1 */
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#define DP_MAR2 0xA /* Multicast Address Register 2 */
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#define DP_MAR3 0xB /* Multicast Address Register 3 */
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#define DP_MAR4 0xC /* Multicast Address Register 4 */
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#define DP_MAR5 0xD /* Multicast Address Register 5 */
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#define DP_MAR6 0xE /* Multicast Address Register 6 */
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#define DP_MAR7 0xF /* Multicast Address Register 7 */
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/* Bits in dp_cr */
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#define CR_STP 0x01 /* Stop: software reset */
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#define CR_STA 0x02 /* Start: activate NIC */
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#define CR_TXP 0x04 /* Transmit Packet */
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#define CR_DMA 0x38 /* Mask for DMA control */
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#define CR_DM_NOP 0x00 /* DMA: No Operation */
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#define CR_DM_RR 0x08 /* DMA: Remote Read */
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#define CR_DM_RW 0x10 /* DMA: Remote Write */
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#define CR_DM_SP 0x18 /* DMA: Send Packet */
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#define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */
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#define CR_PS 0xC0 /* Mask for Page Select */
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#define CR_PS_P0 0x00 /* Register Page 0 */
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#define CR_PS_P1 0x40 /* Register Page 1 */
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#define CR_PS_P2 0x80 /* Register Page 2 */
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#define CR_PS_T1 0xC0 /* Test Mode Register Map */
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/* Bits in dp_isr */
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#define ISR_PRX 0x01 /* Packet Received with no errors */
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#define ISR_PTX 0x02 /* Packet Transmitted with no errors */
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#define ISR_RXE 0x04 /* Receive Error */
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#define ISR_TXE 0x08 /* Transmit Error */
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#define ISR_OVW 0x10 /* Overwrite Warning */
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#define ISR_CNT 0x20 /* Counter Overflow */
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#define ISR_RDC 0x40 /* Remote DMA Complete */
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#define ISR_RST 0x80 /* Reset Status */
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/* Bits in dp_imr */
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#define IMR_PRXE 0x01 /* Packet Received iEnable */
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#define IMR_PTXE 0x02 /* Packet Transmitted iEnable */
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#define IMR_RXEE 0x04 /* Receive Error iEnable */
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#define IMR_TXEE 0x08 /* Transmit Error iEnable */
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#define IMR_OVWE 0x10 /* Overwrite Warning iEnable */
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#define IMR_CNTE 0x20 /* Counter Overflow iEnable */
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#define IMR_RDCE 0x40 /* DMA Complete iEnable */
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/* Bits in dp_dcr */
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#define DCR_WTS 0x01 /* Word Transfer Select */
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#define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */
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#define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */
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#define DCR_BOS 0x02 /* Byte Order Select */
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#define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */
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#define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */
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#define DCR_LAS 0x04 /* Long Address Select */
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#define DCR_BMS 0x08 /* Burst Mode Select
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* Called Loopback Select (LS) in
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* later manuals. Should be set. */
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#define DCR_AR 0x10 /* Autoinitialize Remote */
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#define DCR_FTS 0x60 /* Fifo Threshold Select */
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#define DCR_2BYTES 0x00 /* 2 bytes */
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#define DCR_4BYTES 0x40 /* 4 bytes */
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#define DCR_8BYTES 0x20 /* 8 bytes */
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#define DCR_12BYTES 0x60 /* 12 bytes */
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/* Bits in dp_tcr */
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#define TCR_CRC 0x01 /* Inhibit CRC */
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#define TCR_ELC 0x06 /* Encoded Loopback Control */
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#define TCR_NORMAL 0x00 /* ELC: Normal Operation */
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#define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */
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#define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */
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#define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */
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#define TCR_ATD 0x08 /* Auto Transmit Disable */
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#define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */
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/* Bits in dp_tsr */
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#define TSR_PTX 0x01 /* Packet Transmitted (without error)*/
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#define TSR_DFR 0x02 /* Transmit Deferred, reserved in
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* later manuals. */
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#define TSR_COL 0x04 /* Transmit Collided */
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#define TSR_ABT 0x08 /* Transmit Aborted */
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#define TSR_CRS 0x10 /* Carrier Sense Lost */
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#define TSR_FU 0x20 /* FIFO Underrun */
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#define TSR_CDH 0x40 /* CD Heartbeat */
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#define TSR_OWC 0x80 /* Out of Window Collision */
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/* Bits in tp_rcr */
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#define RCR_SEP 0x01 /* Save Errored Packets */
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#define RCR_AR 0x02 /* Accept Runt Packets */
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#define RCR_AB 0x04 /* Accept Broadcast */
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#define RCR_AM 0x08 /* Accept Multicast */
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#define RCR_PRO 0x10 /* Physical Promiscuous */
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#define RCR_MON 0x20 /* Monitor Mode */
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/* Bits in dp_rsr */
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#define RSR_PRX 0x01 /* Packet Received Intact */
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#define RSR_CRC 0x02 /* CRC Error */
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#define RSR_FAE 0x04 /* Frame Alignment Error */
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#define RSR_FO 0x08 /* FIFO Overrun */
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#define RSR_MPA 0x10 /* Missed Packet */
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#define RSR_PHY 0x20 /* Multicast Address Match */
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#define RSR_DIS 0x40 /* Receiver Disabled */
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#define RSR_DFR 0x80 /* In later manuals: Deferring */
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typedef struct dp_rcvhdr
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{
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u8_t dr_status; /* Copy of rsr */
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u8_t dr_next; /* Pointer to next packet */
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u8_t dr_rbcl; /* Receive Byte Count Low */
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u8_t dr_rbch; /* Receive Byte Count High */
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} dp_rcvhdr_t;
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#define DP_PAGESIZE 256
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/* Some macros to simplify accessing the dp8390 */
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#define inb_reg0(dep, reg) (inb(dep->de_dp8390_port+reg))
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#define outb_reg0(dep, reg, data) (outb(dep->de_dp8390_port+reg, data))
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#define inb_reg1(dep, reg) (inb(dep->de_dp8390_port+reg))
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#define outb_reg1(dep, reg, data) (outb(dep->de_dp8390_port+reg, data))
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/* Software interface to the dp8390 driver */
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struct dpeth;
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struct iovec_dat;
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2006-07-10 14:43:38 +02:00
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struct iovec_dat_s;
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2005-08-05 11:53:08 +02:00
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_PROTOTYPE( typedef void (*dp_initf_t), (struct dpeth *dep) );
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_PROTOTYPE( typedef void (*dp_stopf_t), (struct dpeth *dep) );
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_PROTOTYPE( typedef void (*dp_user2nicf_t), (struct dpeth *dep,
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struct iovec_dat *iovp, vir_bytes offset,
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int nic_addr, vir_bytes count) );
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2006-07-10 14:43:38 +02:00
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_PROTOTYPE( typedef void (*dp_user2nicf_s_t), (struct dpeth *dep,
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struct iovec_dat_s *iovp, vir_bytes offset,
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int nic_addr, vir_bytes count) );
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2005-08-05 11:53:08 +02:00
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_PROTOTYPE( typedef void (*dp_nic2userf_t), (struct dpeth *dep,
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int nic_addr, struct iovec_dat *iovp,
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vir_bytes offset, vir_bytes count) );
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2006-07-10 14:43:38 +02:00
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_PROTOTYPE( typedef void (*dp_nic2userf_s_t), (struct dpeth *dep,
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int nic_addr, struct iovec_dat_s *iovp,
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vir_bytes offset, vir_bytes count) );
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2005-08-05 11:53:08 +02:00
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#if 0
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_PROTOTYPE( typedef void (*dp_getheaderf_t), (struct dpeth *dep,
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int page, struct dp_rcvhdr *h, u16_t *eth_type) );
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#endif
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_PROTOTYPE( typedef void (*dp_getblock_t), (struct dpeth *dep,
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int page, size_t offset, size_t size, void *dst) );
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/* iovectors are handled IOVEC_NR entries at a time. */
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#define IOVEC_NR 16
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typedef int irq_hook_t;
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typedef struct iovec_dat
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{
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iovec_t iod_iovec[IOVEC_NR];
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int iod_iovec_s;
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int iod_proc_nr;
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vir_bytes iod_iovec_addr;
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} iovec_dat_t;
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2006-07-10 14:43:38 +02:00
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typedef struct iovec_dat_s
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{
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iovec_s_t iod_iovec[IOVEC_NR];
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int iod_iovec_s;
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int iod_proc_nr;
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cp_grant_id_t iod_grant;
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vir_bytes iod_iovec_offset;
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} iovec_dat_s_t;
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2005-08-05 11:53:08 +02:00
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#define SENDQ_NR 2 /* Maximum size of the send queue */
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#define SENDQ_PAGES 6 /* 6 * DP_PAGESIZE >= 1514 bytes */
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typedef struct dpeth
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{
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/* The de_base_port field is the starting point of the probe.
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* The conf routine also fills de_linmem and de_irq. If the probe
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* routine knows the irq and/or memory address because they are
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* hardwired in the board, the probe should modify these fields.
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* Futhermore, the probe routine should also fill in de_initf and
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* de_stopf fields with the appropriate function pointers and set
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* de_prog_IO iff programmed I/O is to be used.
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*/
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port_t de_base_port;
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phys_bytes de_linmem;
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2006-07-10 14:43:38 +02:00
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char *de_locmem;
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2005-08-05 11:53:08 +02:00
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int de_irq;
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int de_int_pending;
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irq_hook_t de_hook;
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dp_initf_t de_initf;
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dp_stopf_t de_stopf;
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int de_prog_IO;
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char de_name[sizeof("dp8390#n")];
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/* The initf function fills the following fields. Only cards that do
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* programmed I/O fill in the de_pata_port field.
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* In addition, the init routine has to fill in the sendq data
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* structures.
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*/
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ether_addr_t de_address;
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port_t de_dp8390_port;
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port_t de_data_port;
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int de_16bit;
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int de_ramsize;
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int de_offset_page;
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int de_startpage;
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int de_stoppage;
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#if ENABLE_PCI
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/* PCI config */
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char de_pci; /* TRUE iff PCI device */
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u8_t de_pcibus;
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u8_t de_pcidev;
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u8_t de_pcifunc;
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#endif
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/* Do it yourself send queue */
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struct sendq
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{
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int sq_filled; /* this buffer contains a packet */
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int sq_size; /* with this size */
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int sq_sendpage; /* starting page of the buffer */
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} de_sendq[SENDQ_NR];
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int de_sendq_nr;
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int de_sendq_head; /* Enqueue at the head */
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int de_sendq_tail; /* Dequeue at the tail */
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/* Fields for internal use by the dp8390 driver. */
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int de_flags;
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int de_mode;
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eth_stat_t de_stat;
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2006-07-10 14:43:38 +02:00
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iovec_dat_s_t de_read_iovec_s;
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iovec_dat_s_t de_write_iovec_s;
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iovec_dat_s_t de_tmp_iovec_s;
|
2005-08-05 11:53:08 +02:00
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vir_bytes de_read_s;
|
2010-03-30 16:07:15 +02:00
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|
endpoint_t de_client;
|
2005-08-05 11:53:08 +02:00
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|
message de_sendmsg;
|
2006-07-10 14:43:38 +02:00
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dp_user2nicf_s_t de_user2nicf_s;
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dp_nic2userf_s_t de_nic2userf_s;
|
2005-08-05 11:53:08 +02:00
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|
dp_getblock_t de_getblockf;
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} dpeth_t;
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#define DEI_DEFAULT 0x8000
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#define DEF_EMPTY 0x000
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#define DEF_PACK_SEND 0x001
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#define DEF_PACK_RECV 0x002
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#define DEF_SEND_AVAIL 0x004
|
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#define DEF_READING 0x010
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#define DEF_PROMISC 0x040
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#define DEF_MULTI 0x080
|
|
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#define DEF_BROAD 0x100
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#define DEF_ENABLED 0x200
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#define DEF_STOPPED 0x400
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#define DEM_DISABLED 0x0
|
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#define DEM_SINK 0x1
|
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|
|
#define DEM_ENABLED 0x2
|
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#if !__minix_vmd
|
|
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|
|
#define debug 0 /* Standard Minix lacks debug variable */
|
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|
#endif
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|
|
|
/*
|
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|
* $PchId: dp8390.h,v 1.10 2005/02/10 17:26:06 philip Exp $
|
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*/
|
