184 lines
8.2 KiB
C
184 lines
8.2 KiB
C
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/* Attansic/Atheros L2 FastEthernet driver, by D.C. van Moolenbroek */
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#define ATL2_MMAP_SIZE 0x40000 /* memory-mapped registers */
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/* The first three are configurable to a certain extent; the last is not. */
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#define ATL2_TXD_BUFSIZE 8192 /* TxD ring buffer size */
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#define ATL2_TXS_COUNT 64 /* Tx status ring array size */
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#define ATL2_RXD_COUNT 64 /* Rx descriptors */
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#define ATL2_RXD_SIZE 1536 /* Rx element size */
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#define ATL2_MASTER_REG 0x1400 /* master register */
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# define ATL2_MASTER_SOFT_RESET 0x00000001 /* soft reset */
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# define ATL2_MASTER_IMT_EN 0x00000004 /* IMT enabled */
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#define ATL2_RESET_NTRIES 100 /* #tries to wait for reset */
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#define ATL2_RESET_DELAY 10 /* delay (us) between tries */
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#define ATL2_PHY_ENABLE_REG 0x140c /* PHY enable register */
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# define ATL2_PHY_ENABLE 1 /* enable PHY */
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#define ATL2_IDLE_REG 0x1410 /* idle status register */
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#define ATL2_IDLE_NTRIES 100 /* #tries to wait for idle */
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#define ATL2_IDLE_DELAY 100 /* delay (us) between tries */
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#define ATL2_HWADDR0_REG 0x1488 /* Hardware address (part 0) */
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#define ATL2_HWADDR1_REG 0x148c /* Hardware address (part 1) */
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#define ATL2_ISR_REG 0x1600 /* interrupt status register */
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# define ATL2_ISR_RXF_OVERFLOW 0x00000004 /* RxF overflow */
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# define ATL2_ISR_TXF_UNDERRUN 0x00000008 /* TxF underrun */
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# define ATL2_ISR_TXS_OVERFLOW 0x00000010 /* TxS overflow */
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# define ATL2_ISR_RXS_OVERFLOW 0x00000020 /* RxS overflow */
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# define ATL2_ISR_TXD_UNDERRUN 0x00000080 /* TxD underrun */
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# define ATL2_ISR_RXD_OVERFLOW 0x00000100 /* RxD overflow */
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# define ATL2_ISR_DMAR_TIMEOUT 0x00000200 /* DMA read timeout */
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# define ATL2_ISR_DMAW_TIMEOUT 0x00000400 /* DMA write timeout */
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# define ATL2_ISR_TXS_UPDATED 0x00010000 /* Tx status updated */
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# define ATL2_ISR_RXD_UPDATED 0x00020000 /* Rx status updated */
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# define ATL2_ISR_TX_EARLY 0x00040000 /* Tx started xmit */
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# define ATL2_ISR_PHY_LINKDOWN 0x10000000 /* PHY link down */
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# define ATL2_ISR_DISABLE 0x80000000 /* disable intrs */
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# define ATL2_ISR_TX_EVENT (ATL2_ISR_TXF_UNDERRUN | \
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ATL2_ISR_TXS_OVERFLOW | \
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ATL2_ISR_TXD_UNDERRUN | \
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ATL2_ISR_TXS_UPDATED | \
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ATL2_ISR_TX_EARLY)
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# define ATL2_ISR_RX_EVENT (ATL2_ISR_RXF_OVERFLOW | \
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ATL2_ISR_RXS_OVERFLOW | \
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ATL2_ISR_RXD_OVERFLOW | \
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ATL2_ISR_RXD_UPDATED)
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#define ATL2_IMR_REG 0x1604 /* interrupt mask register */
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# define ATL2_IMR_DEFAULT (ATL2_ISR_DMAR_TIMEOUT | \
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ATL2_ISR_DMAW_TIMEOUT | \
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ATL2_ISR_TXS_UPDATED | \
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ATL2_ISR_RXD_UPDATED | \
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ATL2_ISR_PHY_LINKDOWN)
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#define ATL2_MAC_REG 0x1480 /* MAC config register */
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# define ATL2_MAC_TX_EN 0x00000001 /* enable transmit */
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# define ATL2_MAC_RX_EN 0x00000002 /* enable receive */
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# define ATL2_MAC_PROMISC_EN 0x00008000 /* promiscuous */
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# define ATL2_MAC_MCAST_EN 0x02000000 /* multicast */
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# define ATL2_MAC_BCAST_EN 0x04000000 /* broadcast */
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# define ATL2_MAC_DEFAULT 0x28001cec /* (magic) */
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#define ATL2_MHT0_REG 0x1490 /* multicast hash table bits */
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#define ATL2_MHT1_REG 0x1494 /* 64 slots in total */
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#define ATL2_DMAREAD_REG 0x1580 /* read DMA config register */
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# define ATL2_DMAREAD_EN 1 /* read DMA enabled */
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#define ATL2_DMAWRITE_REG 0x15a0 /* write DMA config register */
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# define ATL2_DMAWRITE_EN 1 /* write DMA enabled */
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#define ATL2_DESC_ADDR_HI_REG 0x1540 /* high 32 bits of addresses */
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#define ATL2_TXD_ADDR_LO_REG 0x1544 /* low 32 bits of TxD base */
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#define ATL2_TXD_BUFSIZE_REG 0x1548 /* size of TxD ring buffer */
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#define ATL2_TXS_ADDR_LO_REG 0x154c /* low 32 bits of TxS base */
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#define ATL2_TXS_COUNT_REG 0x1550 /* number of TxS descriptors */
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#define ATL2_RXD_ADDR_LO_REG 0x1554 /* low 32 bits of RxD base */
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#define ATL2_RXD_COUNT_REG 0x1558 /* number of RxD descriptors */
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#define ATL2_IFG_REG 0x1484 /* inter-frame gap config */
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# define ATL2_IFG_DEFAULT 0x60405060 /* (magic) */
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#define ATL2_HDPX_REG 0x1498 /* half-duplex mode config */
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# define ATL2_HDPX_DEFAULT 0x07a1f037 /* (magic) */
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#define ATL2_IMT_REG 0x1408 /* intr moderation timer */
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# define ATL2_IMT_DEFAULT 100 /* 200 us */
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#define ATL2_ICT_REG 0x140e /* intr clearing timer */
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# define ATL2_ICT_DEFAULT 50000 /* 100 ms */
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#define ATL2_MTU_REG 0x149c /* MTU config */
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# define ATL2_MTU_DEFAULT ETH_MAX_PACK_SIZE_TAGGED
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#define ATL2_CUT_THRESH_REG 0x1590 /* cut-through config */
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# define ATL2_CUT_THRESH_DEFAULT 0x177 /* (magic) */
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#define ATL2_FLOW_THRESH_HI_REG 0x15a8 /* RxD overflow hi watermark */
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#define ATL2_FLOW_THRESH_LO_REG 0x15aa /* RxD overflow lo watermark */
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#define ATL2_TXD_IDX_REG 0x15f0 /* TxD read index */
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#define ATL2_RXD_IDX_REG 0x15f4 /* RxD write index */
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#define ATL2_LTSSM_TESTMODE_REG 0x12fc /* PCIE configuration */
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#define ATL2_LTSSM_TESTMODE_DEFAULT 0x6500 /* (magic) */
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#define ATL2_DLL_TX_CTRL_REG 0x1104 /* PCIE configuration */
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#define ATL2_DLL_TX_CTRL_DEFAULT 0x0568 /* (magic) */
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#define ATL2_VPD_CAP_REG 0x6c /* VPD command register */
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# define ATL2_VPD_CAP_ADDR_SHIFT 16
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# define ATL2_VPD_CAP_ADDR_MASK 0x7fff0000
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# define ATL2_VPD_CAP_DONE 0x80000000
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#define ATL2_VPD_DATA_REG 0x70 /* VPD data register */
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#define ATL2_SPICTL_REG 0x200 /* SPI control register */
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# define ATL2_SPICTL_VPD_EN 0x2000 /* enable VPD */
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#define ATL2_VPD_REGBASE 0x100 /* VPD register base */
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#define ATL2_VPD_NREGS 64 /* number of VPD registers */
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#define ATL2_VPD_SIG_MASK 0xff /* signature mask */
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#define ATL2_VPD_SIG 0x5a /* VPD entry signature */
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#define ATL2_VPD_REG_SHIFT 16 /* key shift */
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#define ATL2_VPD_NTRIES 10 /* #tries to read from VPD */
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#define ATL2_VPD_DELAY 2000 /* delay (us) between tries */
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#define ATL2_MDIO_REG 0x1414 /* Management Data I/O reg */
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# define ATL2_MDIO_ADDR_SHIFT 16 /* register address */
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# define ATL2_MDIO_ADDR_MASK 0x001f0000 /* (shift and mask) */
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# define ATL2_MDIO_READ 0x00200000 /* read operation */
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# define ATL2_MDIO_SUP_PREAMBLE 0x00400000 /* suppress preamble */
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# define ATL2_MDIO_START 0x00800000 /* initiate xfer */
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# define ATL2_MDIO_CLK_25_4 0x00000000 /* 25MHz, 4bit */
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# define ATL2_MDIO_BUSY 0x08000000 /* in progress */
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# define ATL2_MDIO_DATA_MASK 0x0000ffff /* result data mask */
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#define ATL2_MDIO_NTRIES 10 /* #tries to access MDIO */
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#define ATL2_MDIO_DELAY 2 /* delay (us) between tries */
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#define ATL2_MII_BMSR 1 /* basic mode status reg */
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# define ATL2_MII_BMSR_LSTATUS 0x0004 /* link status */
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#define ATL2_MII_PSSR 17 /* PHY specific status reg */
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# define ATL2_MII_PSSR_RESOLVED 0x0800 /* speed/duplex OK */
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# define ATL2_MII_PSSR_DUPLEX 0x2000 /* full duplex */
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# define ATL2_MII_PSSR_SPEED 0xc000 /* link speed */
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# define ATL2_MII_PSSR_10 0x0000 /* 10Mbps */
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# define ATL2_MII_PSSR_100 0x4000 /* 100Mbps */
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# define ATL2_MII_PSSR_1000 0x8000 /* 1000Mbps */
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#define ATL2_RXD_SIZE_MASK 0x000007ff /* packet size mask */
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#define ATL2_RXD_SUCCESS 0x00010000 /* successful receipt */
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#define ATL2_RXD_BCAST 0x00020000 /* broadcast frame */
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#define ATL2_RXD_MCAST 0x00040000 /* multicast frame */
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#define ATL2_RXD_PAUSE 0x00080000 /* pause frame */
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#define ATL2_RXD_CTRL 0x00100000 /* control frame */
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#define ATL2_RXD_CRCERR 0x00200000 /* invalid frame CRC */
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#define ATL2_RXD_CODEERR 0x00400000 /* invalid opcode */
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#define ATL2_RXD_RUNT 0x00800000 /* short frame */
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#define ATL2_RXD_FRAG 0x01000000 /* collision fragment */
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#define ATL2_RXD_TRUNC 0x02000000 /* frame truncated */
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#define ATL2_RXD_ALIGN 0x04000000 /* frame align error */
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#define ATL2_RXD_UPDATE 0x80000000 /* updated by device */
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#define ATL2_TXS_SIZE_MASK 0x000007ff /* packet size mask */
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#define ATL2_TXS_SUCCESS 0x00010000 /* successful xmit */
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#define ATL2_TXS_BCAST 0x00020000 /* broadcast frame */
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#define ATL2_TXS_MCAST 0x00040000 /* multicast frame */
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#define ATL2_TXS_PAUSE 0x00080000 /* pause frame */
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#define ATL2_TXS_CTRL 0x00100000 /* control frame */
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#define ATL2_TXS_DEFER 0x00200000 /* deferred transmit */
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#define ATL2_TXS_EXCDEFER 0x00400000 /* excess defer */
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#define ATL2_TXS_SINGLECOL 0x00800000 /* single collision */
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#define ATL2_TXS_MULTICOL 0x01000000 /* multi collisions */
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#define ATL2_TXS_LATECOL 0x02000000 /* late collision */
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#define ATL2_TXS_ABORTCOL 0x04000000 /* collision abort */
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#define ATL2_TXS_UNDERRUN 0x08000000 /* buffer underrun */
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#define ATL2_TXS_UPDATE 0x80000000 /* updated by device */
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