170 lines
6.1 KiB
ArmAsm
170 lines
6.1 KiB
ArmAsm
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/* $NetBSD: compat___sigtramp1.S,v 1.1 2005/10/16 04:41:34 christos Exp $ */
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/*
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* Copyright (c) 1996-2002 Eduardo Horvath
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* Copyright (c) 1996 Paul Kranenburg
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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* This product includes software developed by Harvard University.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Harvard University.
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* This product includes software developed by Paul Kranenburg.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "SYS.h"
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#define _LOCORE
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#include <machine/frame.h>
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#include <machine/fsr.h>
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#include <machine/ctlreg.h>
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#include <machine/psl.h>
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.register %g2,#ignore
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.register %g3,#ignore
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/*
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* When this code is run, the stack looks like:
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* [%sp] 128 bytes to which registers can be dumped
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* [%sp + 128] signal number (goes in %o0)
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* [%sp + 128 + 4] signal code (goes in %o1)
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* [%sp + 128 + 8] first word of saved state (sigcontext)
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* .
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* .
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* .
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* [%sp + NNN] last word of saved state
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* (followed by previous stack contents or top of signal stack).
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* The address of the function to call is in %g1; the old %g1 and %o0
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* have already been saved in the sigcontext. We are running in a clean
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* window, all previous windows now being saved to the stack.
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*
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* Note that [%sp + 128 + 8] == %sp + 128 + 16. The copy at %sp+128+8
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* will eventually be removed, with a hole left in its place, if things
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* work out.
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*/
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ENTRY_NOPROFILE(__sigtramp_sigcontext_1)
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/*
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* XXX the `save' and `restore' below are unnecessary: should
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* replace with simple arithmetic on %sp
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*
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* Make room on the stack for 64 %f registers + %fsr. This comes
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* out to 64*4+8 or 264 bytes, but this must be aligned to a multiple
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* of 64, or 320 bytes.
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*/
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save %sp, -CC64FSZ - 320, %sp
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mov %g2, %l2 /* save globals in %l registers */
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mov %g3, %l3
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mov %g4, %l4
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mov %g5, %l5
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mov %g6, %l6
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mov %g7, %l7
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/*
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* Saving the fpu registers is expensive, so do it iff it is
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* enabled and dirty.
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*/
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rd %fprs, %l0
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btst FPRS_DL|FPRS_DU, %l0 /* All clean? */
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bz,pt %icc, 2f
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btst FPRS_DL, %l0 /* test dl */
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bz,pt %icc, 1f
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btst FPRS_DU, %l0 /* test du */
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/* fpu is enabled, oh well */
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stx %fsr, [%sp + CC64FSZ + BIAS + 0]
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add %sp, BIAS+CC64FSZ+BLOCK_SIZE, %l0 /* Generate a pointer so */
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andn %l0, BLOCK_ALIGN, %l0 /* we can do a block store */
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stda %f0, [%l0] ASI_BLK_P
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inc BLOCK_SIZE, %l0
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stda %f16, [%l0] ASI_BLK_P
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1:
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bz,pt %icc, 2f
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add %sp, BIAS+CC64FSZ+BLOCK_SIZE, %l0 /* Generate a pointer so */
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andn %l0, BLOCK_ALIGN, %l0 /* we can do a block store */
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add %l0, 2*BLOCK_SIZE, %l0 /* and skip what we already stored */
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stda %f32, [%l0] ASI_BLK_P
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inc BLOCK_SIZE, %l0
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stda %f48, [%l0] ASI_BLK_P
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2:
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membar #Sync
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rd %y, %l1 /* in any case, save %y */
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lduw [%fp + BIAS + 128], %o0 /* sig */
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lduw [%fp + BIAS + 128 + 4], %o1 /* code */
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call %g1 /* call handler */
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add %fp, BIAS + 128 + 8, %o2 /* scp */
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/*
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* Now that the handler has returned, re-establish all the state
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* we just saved above, then do a sigreturn.
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*/
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btst 3, %l0 /* All clean? */
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bz,pt %icc, 2f
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btst 1, %l0 /* test dl */
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bz,pt %icc, 1f
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btst 2, %l0 /* test du */
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ldx [%sp + CC64FSZ + BIAS + 0], %fsr
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add %sp, BIAS+CC64FSZ+BLOCK_SIZE, %l0 /* Generate a pointer so */
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andn %l0, BLOCK_ALIGN, %l0 /* we can do a block load */
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ldda [%l0] ASI_BLK_P, %f0
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inc BLOCK_SIZE, %l0
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ldda [%l0] ASI_BLK_P, %f16
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1:
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bz,pt %icc, 2f
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wr %l1, %g0, %y /* in any case, restore %y */
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add %sp, BIAS+CC64FSZ+BLOCK_SIZE, %l0 /* Generate a pointer so */
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andn %l0, BLOCK_ALIGN, %l0 /* we can do a block load */
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inc 2*BLOCK_SIZE, %l0 /* and skip what we already loaded */
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ldda [%l0] ASI_BLK_P, %f32
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inc BLOCK_SIZE, %l0
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ldda [%l0] ASI_BLK_P, %f48
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2:
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mov %l2, %g2
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mov %l3, %g3
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mov %l4, %g4
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mov %l5, %g5
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mov %l6, %g6
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mov %l7, %g7
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membar #Sync
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/* get registers back and set syscall # */
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restore %g0, SYS_compat_16___sigreturn14, %g1
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add %sp, BIAS + 128 + 8, %o0 /* compute scp */
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t ST_SYSCALL /* call sigreturn */
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mov SYS_exit, %g1 /* exit with errno */
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t ST_SYSCALL /* if sigreturn fails */
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