142 lines
4.8 KiB
C
142 lines
4.8 KiB
C
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/* $NetBSD: i82093reg.h,v 1.3 2011/08/17 14:55:11 dyoung Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by RedBack Networks Inc.
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*
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* Author: Bill Sommerfeld
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Typically, the first apic lives here.
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*/
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#define IOAPIC_BASE_DEFAULT 0xfec00000
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#define IOAPIC_MSIADDR_BASE 0xfee00000
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#define IOAPIC_MSIADDR_DSTID_MASK __BITS(19, 12)
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#define IOAPIC_MSIADDR_RSVD0_MASK __BITS(11, 4)
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#define IOAPIC_MSIADDR_RH __BIT(3)
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#define IOAPIC_MSIADDR_DM __BIT(2)
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#define IOAPIC_MSIADDR_RSVD1_MASK __BITS(1, 0)
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#define IOAPIC_MSIDATA_VECTOR_MASK __BITS(7, 0)
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#define IOAPIC_MSIDATA_DM_MASK __BITS(10, 8)
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#define IOAPIC_MSIDATA_DM_FIXED __SHIFTIN(0, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_DM_LOPRI __SHIFTIN(1, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_DM_SMI __SHIFTIN(2, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_DM_RSVD0 __SHIFTIN(3, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_DM_NMI __SHIFTIN(4, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_DM_INIT __SHIFTIN(5, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_DM_RSVD1 __SHIFTIN(6, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_DM_EXTINT __SHIFTIN(7, IOAPIC_MSIDATA_DM_MASK)
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#define IOAPIC_MSIDATA_RSVD0_MASK __BITS(13, 11)
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#define IOAPIC_MSIDATA_LEVEL_MASK __BIT(14)
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#define IOAPIC_MSIDATA_LEVEL_DEASSERT __SHIFTIN(0, IOAPIC_MSIDATA_LEVEL_MASK)
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#define IOAPIC_MSIDATA_LEVEL_ASSERT __SHIFTIN(1, IOAPIC_MSIDATA_LEVEL_MASK)
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#define IOAPIC_MSIDATA_TRGMODE_MASK __BIT(15)
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#define IOAPIC_MSIDATA_TRGMODE_EDGE \
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__SHIFTIN(0, IOAPIC_MSIDATA_TRGMODE_MASK)
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#define IOAPIC_MSIDATA_TRGMODE_LEVEL \
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__SHIFTIN(1, IOAPIC_MSIDATA_TRGMODE_MASK)
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#define IOAPIC_MSIDATA_RSVD1_MASK __BITS(31, 16)
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/*
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* Memory-space registers.
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*/
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/*
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* The externally visible registers are all 32 bits wide;
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* store the register number of interest in IOAPIC_REG, and store/fetch
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* the real value in IOAPIC_DATA.
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*/
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#define IOAPIC_REG 0x0000
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#define IOAPIC_DATA 0x0010
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/*
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* Internal I/O APIC registers.
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*/
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#define IOAPIC_ID 0x00
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#define IOAPIC_ID_SHIFT 24
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#define IOAPIC_ID_MASK 0x0f000000
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/* Version, and maximum interrupt pin number. */
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#define IOAPIC_VER 0x01
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#define IOAPIC_VER_SHIFT 0
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#define IOAPIC_VER_MASK 0x000000ff
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#define IOAPIC_MAX_SHIFT 16
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#define IOAPIC_MAX_MASK 0x00ff0000
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/*
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* Arbitration ID. Same format as IOAPIC_ID register.
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*/
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#define IOAPIC_ARB 0x02
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/*
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* Redirection table registers.
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*/
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#define IOAPIC_REDHI(pin) (0x11 + ((pin)<<1))
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#define IOAPIC_REDLO(pin) (0x10 + ((pin)<<1))
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#define IOAPIC_REDHI_DEST_SHIFT 24 /* destination. */
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#define IOAPIC_REDHI_DEST_MASK 0xff000000
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#define IOAPIC_REDLO_MASK 0x00010000 /* 0=enabled; 1=masked */
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#define IOAPIC_REDLO_LEVEL 0x00008000 /* 0=edge, 1=level */
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#define IOAPIC_REDLO_RIRR 0x00004000 /* remote IRR; read only */
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#define IOAPIC_REDLO_ACTLO 0x00002000 /* 0=act. hi; 1=act. lo */
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#define IOAPIC_REDLO_DELSTS 0x00001000 /* 0=idle; 1=send pending */
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#define IOAPIC_REDLO_DSTMOD 0x00000800 /* 0=physical; 1=logical */
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#define IOAPIC_REDLO_DEL_MASK 0x00000700 /* del. mode mask */
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#define IOAPIC_REDLO_DEL_SHIFT 8
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#define IOAPIC_REDLO_DEL_FIXED 0
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#define IOAPIC_REDLO_DEL_LOPRI 1
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#define IOAPIC_REDLO_DEL_SMI 2
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#define IOAPIC_REDLO_DEL_NMI 4
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#define IOAPIC_REDLO_DEL_INIT 5
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#define IOAPIC_REDLO_DEL_EXTINT 7
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#define IOAPIC_REDLO_VECTOR_MASK 0x000000ff /* delivery vector */
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#define IMCR_ADDR 0x22
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#define IMCR_DATA 0x23
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#define IMCR_REGISTER 0x70
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#define IMCR_PIC 0x00
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#define IMCR_APIC 0x01
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