56 lines
2.4 KiB
C
56 lines
2.4 KiB
C
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#ifndef _ARM_CPU_H_
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#define _ARM_CPU_H_
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/* xPSR - Program Status Registers */
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#define PSR_T (1 << 5) /* Thumb execution state bit */
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#define PSR_F (1 << 6) /* FIQ mask bit */
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#define PSR_I (1 << 7) /* IRQ mask bit */
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#define PSR_A (1 << 8) /* Asynchronous abort mask bit */
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#define PSR_E (1 << 9) /* Endianness execution state bit */
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#define PSR_J (1 << 24) /* Jazelle bit */
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#define PSR_Q (1 << 27) /* Cumulative saturation bit */
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#define PSR_V (1 << 28) /* Overflow condition flag */
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#define PSR_C (1 << 29) /* Carry condition flag */
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#define PSR_Z (1 << 30) /* Zero condition flag */
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#define PSR_N (1 << 31) /* Negative condition flag */
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#define PSR_MODE_MASK 0x0000001F /* Mode field mask */
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#define MODE_USR 0x10 /* User mode */
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#define MODE_FIQ 0x11 /* FIQ mode */
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#define MODE_IRQ 0x12 /* IRQ mode */
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#define MODE_SVC 0x13 /* Supervisor mode */
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#define MODE_MON 0x16 /* Monitor mode */
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#define MODE_ABT 0x17 /* Abort mode */
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#define MODE_HYP 0x1A /* Hyp mode */
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#define MODE_UND 0x1B /* Undefined mode */
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#define MODE_SYS 0x1F /* System mode */
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/* SCTLR - System Control Register */
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#define SCTLR_M (1 << 0) /* MMU enable */
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#define SCTLR_A (1 << 1) /* Alignment check enable */
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#define SCTLR_C (1 << 2) /* Data and Unified Cache enable */
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#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
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#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
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#define SCTLR_Z (1 << 11) /* Branch prediction enable */
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#define SCTLR_I (1 << 12) /* Instruction cache enable */
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#define SCTLR_V (1 << 13) /* (High) Vectors bit */
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#define SCTLR_RR (1 << 14) /* Round Robin (cache) select */
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#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
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#define SCTLR_FI (1 << 21) /* Fast interrupts configuration enable */
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#define SCTLR_VE (1 << 24) /* Interrupt Vectors Enable */
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#define SCTLR_EE (1 << 25) /* Exception Endianness */
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#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ (NMFI) support */
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#define SCTLR_TRE (1 << 28) /* TEX remap enable */
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#define SCTLR_AFE (1 << 29) /* Access flag enable */
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#define SCTLR_TE (1 << 30) /* Thumb Exception enable */
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/* ACTLR - Auxiliary Control Register */
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#define A8_ACTLR_L1ALIAS (1 << 0) /* L1 Dcache hw alias check enable */
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#define A8_ACTLR_L2EN (1 << 1) /* L2 cache enable */
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#define A8_ACTLR_L1RSTDIS (1 << 30) /* L1 hw reset disable */
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#define A8_ACTLR_L2RSTDIS (1 << 31) /* L2 hw reset disable */
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#endif /* _ARM_CPU_H_ */
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