ff5718f042
This patch is the result of static analysis identifying a number of memory leaks. The leaks are all benign as they are a result of not deallocating memory in the desctructor. The fix still has value as it removes false positives in the static analysis.
557 lines
17 KiB
C++
557 lines
17 KiB
C++
/*
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* Copyright (c) 2011-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2011 Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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* Rick Strong
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*/
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#include <iostream>
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#include <sstream>
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#include <string>
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#include "arch/tlb.hh"
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#include "base/loader/symtab.hh"
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#include "base/cprintf.hh"
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#include "base/misc.hh"
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/cpuevent.hh"
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#include "cpu/profile.hh"
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#include "cpu/thread_context.hh"
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#include "debug/SyscallVerbose.hh"
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#include "params/BaseCPU.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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#include "sim/sim_events.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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// Hack
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#include "sim/stat_control.hh"
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using namespace std;
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vector<BaseCPU *> BaseCPU::cpuList;
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// This variable reflects the max number of threads in any CPU. Be
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// careful to only use it once all the CPUs that you care about have
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// been initialized
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int maxThreadsPerCPU = 1;
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CPUProgressEvent::CPUProgressEvent(BaseCPU *_cpu, Tick ival)
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: Event(Event::Progress_Event_Pri), _interval(ival), lastNumInst(0),
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cpu(_cpu), _repeatEvent(true)
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{
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if (_interval)
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cpu->schedule(this, curTick() + _interval);
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}
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void
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CPUProgressEvent::process()
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{
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Counter temp = cpu->totalOps();
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#ifndef NDEBUG
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double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
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DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
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"%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
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ipc);
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ipc = 0.0;
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#else
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cprintf("%lli: %s progress event, total committed:%i, progress insts "
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"committed: %lli\n", curTick(), cpu->name(), temp,
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temp - lastNumInst);
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#endif
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lastNumInst = temp;
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if (_repeatEvent)
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cpu->schedule(this, curTick() + _interval);
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}
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const char *
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CPUProgressEvent::description() const
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{
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return "CPU Progress";
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}
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BaseCPU::BaseCPU(Params *p, bool is_checker)
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: MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
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_instMasterId(p->system->getMasterId(name() + ".inst")),
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_dataMasterId(p->system->getMasterId(name() + ".data")),
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interrupts(p->interrupts),
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numThreads(p->numThreads), system(p->system),
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phase(p->phase)
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{
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// currentTick = curTick();
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// if Python did not provide a valid ID, do it here
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if (_cpuId == -1 ) {
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_cpuId = cpuList.size();
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}
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// add self to global list of CPUs
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cpuList.push_back(this);
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DPRINTF(SyscallVerbose, "Constructing CPU with id %d\n", _cpuId);
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if (numThreads > maxThreadsPerCPU)
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maxThreadsPerCPU = numThreads;
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// allocate per-thread instruction-based event queues
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comInstEventQueue = new EventQueue *[numThreads];
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for (ThreadID tid = 0; tid < numThreads; ++tid)
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comInstEventQueue[tid] =
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new EventQueue("instruction-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_insts_any_thread != 0) {
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const char *cause = "a thread reached the max instruction count";
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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Event *event = new SimLoopExitEvent(cause, 0);
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comInstEventQueue[tid]->schedule(event, p->max_insts_any_thread);
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}
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}
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if (p->max_insts_all_threads != 0) {
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const char *cause = "all threads reached the max instruction count";
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = numThreads;
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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Event *event = new CountedExitEvent(cause, *counter);
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comInstEventQueue[tid]->schedule(event, p->max_insts_all_threads);
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}
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}
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// allocate per-thread load-based event queues
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comLoadEventQueue = new EventQueue *[numThreads];
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for (ThreadID tid = 0; tid < numThreads; ++tid)
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comLoadEventQueue[tid] = new EventQueue("load-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_loads_any_thread != 0) {
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const char *cause = "a thread reached the max load count";
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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Event *event = new SimLoopExitEvent(cause, 0);
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comLoadEventQueue[tid]->schedule(event, p->max_loads_any_thread);
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}
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}
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if (p->max_loads_all_threads != 0) {
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const char *cause = "all threads reached the max load count";
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = numThreads;
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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Event *event = new CountedExitEvent(cause, *counter);
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comLoadEventQueue[tid]->schedule(event, p->max_loads_all_threads);
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}
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}
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functionTracingEnabled = false;
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if (p->function_trace) {
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const string fname = csprintf("ftrace.%s", name());
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functionTraceStream = simout.find(fname);
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if (!functionTraceStream)
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functionTraceStream = simout.create(fname);
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currentFunctionStart = currentFunctionEnd = 0;
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functionEntryTick = p->function_trace_start;
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if (p->function_trace_start == 0) {
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functionTracingEnabled = true;
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} else {
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typedef EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace> wrap;
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Event *event = new wrap(this, true);
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schedule(event, p->function_trace_start);
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}
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}
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// The interrupts should always be present unless this CPU is
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// switched in later or in case it is a checker CPU
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if (!params()->defer_registration && !is_checker) {
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if (interrupts) {
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interrupts->setCPU(this);
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} else {
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fatal("CPU %s has no interrupt controller.\n"
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"Ensure createInterruptController() is called.\n", name());
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}
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}
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if (FullSystem) {
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profileEvent = NULL;
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if (params()->profile)
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profileEvent = new ProfileEvent(this, params()->profile);
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}
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tracer = params()->tracer;
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}
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void
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BaseCPU::enableFunctionTrace()
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{
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functionTracingEnabled = true;
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}
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BaseCPU::~BaseCPU()
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{
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delete profileEvent;
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delete[] comLoadEventQueue;
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delete[] comInstEventQueue;
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}
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void
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BaseCPU::init()
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{
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if (!params()->defer_registration)
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registerThreadContexts();
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}
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void
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BaseCPU::startup()
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{
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if (FullSystem) {
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if (!params()->defer_registration && profileEvent)
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schedule(profileEvent, curTick());
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}
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if (params()->progress_interval) {
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Tick num_ticks = ticks(params()->progress_interval);
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new CPUProgressEvent(this, num_ticks);
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}
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}
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void
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BaseCPU::regStats()
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{
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using namespace Stats;
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numCycles
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.name(name() + ".numCycles")
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.desc("number of cpu cycles simulated")
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;
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numWorkItemsStarted
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.name(name() + ".numWorkItemsStarted")
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.desc("number of work items this cpu started")
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;
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numWorkItemsCompleted
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.name(name() + ".numWorkItemsCompleted")
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.desc("number of work items this cpu completed")
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;
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int size = threadContexts.size();
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if (size > 1) {
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for (int i = 0; i < size; ++i) {
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stringstream namestr;
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ccprintf(namestr, "%s.ctx%d", name(), i);
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threadContexts[i]->regStats(namestr.str());
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}
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} else if (size == 1)
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threadContexts[0]->regStats(name());
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}
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MasterPort &
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BaseCPU::getMasterPort(const string &if_name, int idx)
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{
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// Get the right port based on name. This applies to all the
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// subclasses of the base CPU and relies on their implementation
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// of getDataPort and getInstPort. In all cases there methods
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// return a CpuPort pointer.
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if (if_name == "dcache_port")
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return getDataPort();
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else if (if_name == "icache_port")
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return getInstPort();
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else
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return MemObject::getMasterPort(if_name, idx);
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}
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Tick
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BaseCPU::nextCycle()
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{
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Tick next_tick = curTick() - phase + clock - 1;
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next_tick -= (next_tick % clock);
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next_tick += phase;
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return next_tick;
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}
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Tick
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BaseCPU::nextCycle(Tick begin_tick)
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{
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Tick next_tick = begin_tick;
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if (next_tick % clock != 0)
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next_tick = next_tick - (next_tick % clock) + clock;
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next_tick += phase;
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assert(next_tick >= curTick());
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return next_tick;
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}
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void
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BaseCPU::registerThreadContexts()
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{
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ThreadID size = threadContexts.size();
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for (ThreadID tid = 0; tid < size; ++tid) {
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ThreadContext *tc = threadContexts[tid];
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/** This is so that contextId and cpuId match where there is a
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* 1cpu:1context relationship. Otherwise, the order of registration
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* could affect the assignment and cpu 1 could have context id 3, for
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* example. We may even want to do something like this for SMT so that
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* cpu 0 has the lowest thread contexts and cpu N has the highest, but
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* I'll just do this for now
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*/
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if (numThreads == 1)
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tc->setContextId(system->registerThreadContext(tc, _cpuId));
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else
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tc->setContextId(system->registerThreadContext(tc));
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if (!FullSystem)
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tc->getProcessPtr()->assignThreadContext(tc->contextId());
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}
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}
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int
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BaseCPU::findContext(ThreadContext *tc)
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{
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ThreadID size = threadContexts.size();
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for (ThreadID tid = 0; tid < size; ++tid) {
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if (tc == threadContexts[tid])
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return tid;
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}
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return 0;
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}
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void
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BaseCPU::switchOut()
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{
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if (profileEvent && profileEvent->scheduled())
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deschedule(profileEvent);
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}
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void
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BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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assert(threadContexts.size() == oldCPU->threadContexts.size());
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_cpuId = oldCPU->cpuId();
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ThreadID size = threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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ThreadContext *newTC = threadContexts[i];
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ThreadContext *oldTC = oldCPU->threadContexts[i];
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newTC->takeOverFrom(oldTC);
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CpuEvent::replaceThreadContext(oldTC, newTC);
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assert(newTC->contextId() == oldTC->contextId());
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assert(newTC->threadId() == oldTC->threadId());
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system->replaceThreadContext(newTC, newTC->contextId());
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/* This code no longer works since the zero register (e.g.,
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* r31 on Alpha) doesn't necessarily contain zero at this
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* point.
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if (DTRACE(Context))
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ThreadContext::compare(oldTC, newTC);
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*/
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MasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
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MasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
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MasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
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MasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
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// Move over any table walker ports if they exist
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if (new_itb_port && !new_itb_port->isConnected()) {
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assert(old_itb_port);
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SlavePort &slavePort = old_itb_port->getSlavePort();
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new_itb_port->bind(slavePort);
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}
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if (new_dtb_port && !new_dtb_port->isConnected()) {
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assert(old_dtb_port);
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SlavePort &slavePort = old_dtb_port->getSlavePort();
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new_dtb_port->bind(slavePort);
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}
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// Checker whether or not we have to transfer CheckerCPU
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// objects over in the switch
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CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
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CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
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if (oldChecker && newChecker) {
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MasterPort *old_checker_itb_port =
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oldChecker->getITBPtr()->getMasterPort();
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MasterPort *old_checker_dtb_port =
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oldChecker->getDTBPtr()->getMasterPort();
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MasterPort *new_checker_itb_port =
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newChecker->getITBPtr()->getMasterPort();
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MasterPort *new_checker_dtb_port =
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newChecker->getDTBPtr()->getMasterPort();
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// Move over any table walker ports if they exist for checker
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if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
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assert(old_checker_itb_port);
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SlavePort &slavePort = old_checker_itb_port->getSlavePort();;
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new_checker_itb_port->bind(slavePort);
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}
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if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
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assert(old_checker_dtb_port);
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SlavePort &slavePort = old_checker_dtb_port->getSlavePort();;
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new_checker_dtb_port->bind(slavePort);
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}
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}
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}
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interrupts = oldCPU->interrupts;
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interrupts->setCPU(this);
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if (FullSystem) {
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for (ThreadID i = 0; i < size; ++i)
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threadContexts[i]->profileClear();
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if (profileEvent)
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schedule(profileEvent, curTick());
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}
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// Connect new CPU to old CPU's memory only if new CPU isn't
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// connected to anything. Also connect old CPU's memory to new
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// CPU.
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if (!getInstPort().isConnected()) {
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getInstPort().bind(oldCPU->getInstPort().getSlavePort());
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}
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if (!getDataPort().isConnected()) {
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getDataPort().bind(oldCPU->getDataPort().getSlavePort());
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}
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}
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BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, Tick _interval)
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: cpu(_cpu), interval(_interval)
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{ }
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void
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BaseCPU::ProfileEvent::process()
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{
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ThreadID size = cpu->threadContexts.size();
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for (ThreadID i = 0; i < size; ++i) {
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ThreadContext *tc = cpu->threadContexts[i];
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tc->profileSample();
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}
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cpu->schedule(this, curTick() + interval);
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}
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void
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BaseCPU::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(instCnt);
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interrupts->serialize(os);
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}
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void
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BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(instCnt);
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interrupts->unserialize(cp, section);
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}
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void
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BaseCPU::traceFunctionsInternal(Addr pc)
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{
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if (!debugSymbolTable)
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return;
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// if pc enters different function, print new function symbol and
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// update saved range. Otherwise do nothing.
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if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
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string sym_str;
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bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
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currentFunctionStart,
|
|
currentFunctionEnd);
|
|
|
|
if (!found) {
|
|
// no symbol found: use addr as label
|
|
sym_str = csprintf("0x%x", pc);
|
|
currentFunctionStart = pc;
|
|
currentFunctionEnd = pc + 1;
|
|
}
|
|
|
|
ccprintf(*functionTraceStream, " (%d)\n%d: %s",
|
|
curTick() - functionEntryTick, curTick(), sym_str);
|
|
functionEntryTick = curTick();
|
|
}
|
|
}
|
|
|
|
bool
|
|
BaseCPU::CpuPort::recvTimingResp(PacketPtr pkt)
|
|
{
|
|
panic("BaseCPU doesn't expect recvTiming!\n");
|
|
return true;
|
|
}
|
|
|
|
void
|
|
BaseCPU::CpuPort::recvRetry()
|
|
{
|
|
panic("BaseCPU doesn't expect recvRetry!\n");
|
|
}
|
|
|
|
void
|
|
BaseCPU::CpuPort::recvFunctionalSnoop(PacketPtr pkt)
|
|
{
|
|
// No internal storage to update (in the general case). A CPU with
|
|
// internal storage, e.g. an LSQ that should be part of the
|
|
// coherent memory has to check against stored data.
|
|
}
|