Andreas Sandberg fec2dea5c3 x86: Add support for m5ops through a memory mapped interface ... In order to support m5ops in virtualized environments, we need to use a memory mapped interface. This changeset adds support for that by reserving 0xFFFF0000-0xFFFFFFFF and mapping those to the generic IPR interface for m5ops. The mapping is done in the X86ISA::TLB::finalizePhysical() which means that it just works for all of the CPU models, including virtualized ones.		2013-09-30 12:20:53 +02:00
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Benchmarks.py	configs: add run scripts for ics/gb versions of android and bbench	2012-06-11 11:07:42 -04:00
CacheConfig.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
Caches.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
CpuConfig.py	config: Add a 'kvm' CPU alias	2013-09-30 09:45:43 +02:00
FSConfig.py	x86: Add support for m5ops through a memory mapped interface	2013-09-30 12:20:53 +02:00
MemConfig.py	config: Command line support for multi-channel memory	2013-08-19 03:52:34 -04:00
O3_ARM_v7a.py	config: Update script to set cache line size on system	2013-07-18 08:31:19 -04:00
Options.py	config: Command line support for multi-channel memory	2013-08-19 03:52:34 -04:00
Simulation.py	config: Initialize and check cpt_starttick	2013-09-11 15:34:21 -05:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00