415 lines
45 KiB
Text
415 lines
45 KiB
Text
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---------- Begin Simulation Statistics ----------
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host_inst_rate 2974441 # Simulator instruction rate (inst/s)
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host_mem_usage 381360 # Number of bytes of host memory used
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host_seconds 17.48 # Real time elapsed on the host
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host_tick_rate 1507548482 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 51978646 # Number of instructions simulated
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sim_seconds 0.026345 # Number of seconds simulated
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sim_ticks 26344863500 # Number of ticks simulated
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system.cpu.dcache.LoadLockedReq_accesses::0 100443 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 100443 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits::0 95328 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 95328 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050924 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::0 5115 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 5115 # number of LoadLockedReq misses
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system.cpu.dcache.ReadReq_accesses::0 7808976 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 7808976 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_hits::0 7572677 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 7572677 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_rate::0 0.030260 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::0 236299 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 236299 # number of ReadReq misses
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system.cpu.dcache.StoreCondReq_accesses::0 100442 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 100442 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits::0 100442 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 100442 # number of StoreCondReq hits
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system.cpu.dcache.WriteReq_accesses::0 6664019 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6664019 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_hits::0 6491936 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 6491936 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_rate::0 0.025823 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::0 172083 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 172083 # number of WriteReq misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 34.645976 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses::0 14472995 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 14472995 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
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system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu.dcache.demand_hits::0 14064613 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 14064613 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate::0 0.028217 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.dcache.demand_misses::0 408382 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 408382 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_blocks::0 511.736581 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.999486 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses::0 14472995 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 14472995 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits::0 14064613 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_hits::total 14064613 # number of overall hits
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system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate::0 0.028217 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::0 408382 # number of overall misses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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system.cpu.dcache.overall_misses::total 408382 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 411144 # number of replacements
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system.cpu.dcache.sampled_refs 411656 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 511.736581 # Cycle average of tags in use
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system.cpu.dcache.total_refs 14262224 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 21760500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 380291 # number of writebacks
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system.cpu.dtb.accesses 15497629 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 2239 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 15491993 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 5636 # DTB misses
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system.cpu.dtb.perms_faults 263 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 787 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 8721338 # DTB read accesses
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system.cpu.dtb.read_hits 8716687 # DTB read hits
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system.cpu.dtb.read_misses 4651 # DTB read misses
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system.cpu.dtb.write_accesses 6776291 # DTB write accesses
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system.cpu.dtb.write_hits 6775306 # DTB write hits
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system.cpu.dtb.write_misses 985 # DTB write misses
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system.cpu.icache.ReadReq_accesses::0 41456992 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 41456992 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_hits::0 41024796 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 41024796 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_rate::0 0.010425 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses::0 432196 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 432196 # number of ReadReq misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 94.921959 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses::0 41456992 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 41456992 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
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system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu.icache.demand_hits::0 41024796 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 41024796 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate::0 0.010425 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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system.cpu.icache.demand_misses::0 432196 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 432196 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_blocks::0 476.343594 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.930359 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses::0 41456992 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 41456992 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits::0 41024796 # number of overall hits
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system.cpu.icache.overall_hits::1 0 # number of overall hits
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system.cpu.icache.overall_hits::total 41024796 # number of overall hits
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system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.icache.overall_misses::0 432196 # number of overall misses
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system.cpu.icache.overall_misses::1 0 # number of overall misses
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system.cpu.icache.overall_misses::total 432196 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 431683 # number of replacements
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system.cpu.icache.sampled_refs 432195 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 476.343594 # Cycle average of tags in use
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system.cpu.icache.total_refs 41024796 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 4572561500 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 33762 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.accesses 41458119 # DTB accesses
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.flush_entries 1476 # Number of entries that have been flushed from TLB
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system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 33678 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.hits 41455189 # DTB hits
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system.cpu.itb.inst_accesses 41458119 # ITB inst accesses
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system.cpu.itb.inst_hits 41455189 # ITB inst hits
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system.cpu.itb.inst_misses 2930 # ITB inst misses
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system.cpu.itb.misses 2930 # DTB misses
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 52689728 # number of cpu cycles simulated
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.num_busy_cycles 52689728 # Number of busy cycles
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system.cpu.num_conditional_control_insts 7011782 # number of instructions that are conditional controls
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system.cpu.num_fp_alu_accesses 6058 # Number of float alu accesses
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system.cpu.num_fp_insts 6058 # number of float instructions
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system.cpu.num_fp_register_reads 4226 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
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system.cpu.num_func_calls 1108496 # number of times a function call or return occured
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_insts 51978646 # Number of instructions executed
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system.cpu.num_int_alu_accesses 42407849 # Number of integer alu accesses
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system.cpu.num_int_insts 42407849 # number of integer instructions
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system.cpu.num_int_register_reads 130779000 # number of times the integer registers were read
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system.cpu.num_int_register_writes 34467088 # number of times the integer registers were written
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system.cpu.num_load_insts 9176676 # Number of load instructions
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system.cpu.num_mem_refs 16251075 # number of memory refs
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system.cpu.num_store_insts 7074399 # Number of store instructions
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system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.iocache.avg_refs no_value # Average number of references to valid blocks.
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system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
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system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
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system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
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system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
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system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
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|
system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
|
|
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
|
|
system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
|
|
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::1 0 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 0 # number of demand (read+write) misses
|
|
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
|
|
system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.iocache.overall_hits::0 0 # number of overall hits
|
|
system.iocache.overall_hits::1 0 # number of overall hits
|
|
system.iocache.overall_hits::total 0 # number of overall hits
|
|
system.iocache.overall_miss_latency 0 # number of overall miss cycles
|
|
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
|
|
system.iocache.overall_misses::0 0 # number of overall misses
|
|
system.iocache.overall_misses::1 0 # number of overall misses
|
|
system.iocache.overall_misses::total 0 # number of overall misses
|
|
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.iocache.replacements 0 # number of replacements
|
|
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
|
|
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.iocache.tagsinuse 0 # Cycle average of tags in use
|
|
system.iocache.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks 0 # number of writebacks
|
|
system.l2c.ReadExReq_accesses::0 170242 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 170242 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_hits::0 60575 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 60575 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_miss_rate::0 0.644183 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_misses::0 109667 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 109667 # number of ReadExReq misses
|
|
system.l2c.ReadReq_accesses::0 671513 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::1 7076 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 678589 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_hits::0 650281 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::1 7045 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 657326 # number of ReadReq hits
|
|
system.l2c.ReadReq_miss_rate::0 0.031618 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::1 0.004381 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.035999 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_misses::0 21232 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::1 31 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 21263 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_accesses::0 1841 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 1841 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_hits::0 19 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_miss_rate::0 0.989680 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_misses::0 1822 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 1822 # number of UpgradeReq misses
|
|
system.l2c.Writeback_accesses::0 414053 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 414053 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_hits::0 414053 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 414053 # number of Writeback hits
|
|
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.l2c.avg_refs 6.728889 # Average number of references to valid blocks.
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.demand_accesses::0 841755 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::1 7076 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 848831 # number of demand (read+write) accesses
|
|
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.l2c.demand_hits::0 710856 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::1 7045 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 717901 # number of demand (read+write) hits
|
|
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_rate::0 0.155507 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::1 0.004381 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.159888 # miss rate for demand accesses
|
|
system.l2c.demand_misses::0 130899 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::1 31 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 130930 # number of demand (read+write) misses
|
|
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.occ_blocks::0 5062.983429 # Average occupied blocks per context
|
|
system.l2c.occ_blocks::1 31189.392245 # Average occupied blocks per context
|
|
system.l2c.occ_percent::0 0.077255 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::1 0.475912 # Average percentage of cache occupancy
|
|
system.l2c.overall_accesses::0 841755 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::1 7076 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 848831 # number of overall (read+write) accesses
|
|
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.l2c.overall_hits::0 710856 # number of overall hits
|
|
system.l2c.overall_hits::1 7045 # number of overall hits
|
|
system.l2c.overall_hits::total 717901 # number of overall hits
|
|
system.l2c.overall_miss_latency 0 # number of overall miss cycles
|
|
system.l2c.overall_miss_rate::0 0.155507 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::1 0.004381 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.159888 # miss rate for overall accesses
|
|
system.l2c.overall_misses::0 130899 # number of overall misses
|
|
system.l2c.overall_misses::1 31 # number of overall misses
|
|
system.l2c.overall_misses::total 130930 # number of overall misses
|
|
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.l2c.replacements 97110 # number of replacements
|
|
system.l2c.sampled_refs 129685 # Sample count of references to valid blocks.
|
|
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.l2c.tagsinuse 36252.375674 # Cycle average of tags in use
|
|
system.l2c.total_refs 872636 # Total number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.writebacks 91105 # number of writebacks
|
|
|
|
---------- End Simulation Statistics ----------
|