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gem5/src/mem/cache
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Andreas Hansson fe806a0dd7 mem: Modernise MSHR iterators to C++11 
This patch updates the iterators in the MSHR and MSHR queues to use
C++11 range-based for loops. It also does a bit of additional house
keeping.
2015-03-27 04:55:57 -04:00
..
prefetch mem: Use emplace front/back for deferred packets 2015-03-19 04:06:11 -04:00
tags mem: Clarify usage of latency in the cache 2015-02-11 10:23:36 -05:00
base.cc mem: Tidy up the cache debug messages 2015-03-02 04:00:37 -05:00
base.hh mem: Align all MSHR entries to block boundaries 2015-03-27 04:55:55 -04:00
BaseCache.py mem: Add parameter to reserve MSHR entries for demand access 2014-12-23 09:31:18 -05:00
blk.cc mem: Add support for a security bit in the memory system 2014-01-24 15:29:30 -06:00
blk.hh mem: Remove WriteInvalidate support 2014-12-02 06:08:17 -05:00
cache.cc mem: refactor LRU cache tags and add random replacement tags 2014-07-28 12:23:23 -04:00
cache.hh mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
cache_impl.hh mem: Align all MSHR entries to block boundaries 2015-03-27 04:55:55 -04:00
mshr.cc mem: Modernise MSHR iterators to C++11 2015-03-27 04:55:57 -04:00
mshr.hh mem: Modernise MSHR iterators to C++11 2015-03-27 04:55:57 -04:00
mshr_queue.cc mem: Modernise MSHR iterators to C++11 2015-03-27 04:55:57 -04:00
mshr_queue.hh mem: Align all MSHR entries to block boundaries 2015-03-27 04:55:55 -04:00
SConscript arch: Resurrect the NOISA build target and rename it NULL 2013-09-04 13:22:57 -04:00