gem5/configs/common
2013-01-08 17:12:22 -05:00
..
Benchmarks.py configs: add run scripts for ics/gb versions of android and bbench 2012-06-11 11:07:42 -04:00
CacheConfig.py Regression: Use CPU clock and 32-byte width for L1-L2 bus 2012-10-15 08:08:08 -04:00
Caches.py config: Unify caches used in regressions and adjust L2 MSHRs 2012-10-30 07:44:08 -04:00
cpu2000.py cpu2000: Add missing art benchmark to all 2012-01-09 18:08:20 -06:00
FSConfig.py config: Do not use hardcoded physmem in fs script 2013-01-07 13:05:38 -05:00
O3_ARM_v7a.py cpu: Rename defer_registration->switched_out 2013-01-07 13:05:45 -05:00
Options.py config: Fix description of checkpoint option from cycle to tick 2012-11-19 11:21:09 -05:00
Simulation.py config: Fix issue with changeset: a4739b6f799d. 2013-01-08 17:12:22 -05:00
SysPaths.py make rcS files read from the m5 source directory, not /dist. 2006-11-08 14:10:25 -05:00