fe27f937aa
This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.
The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.
Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.
Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.
Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.
528 lines
14 KiB
C++
528 lines
14 KiB
C++
// -*- mode: c++ -*-
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// Copyright (c) 2012-2013 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Mbou Eyole
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// Giacomo Gabrielli
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let {{
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simd64EnabledCheckCode = vfp64EnabledCheckCode
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}};
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def template NeonX2RegOpDeclare {{
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template <class _Element>
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class %(class_name)s : public %(base_class)s
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{
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protected:
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typedef _Element Element;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2)
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{
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%(constructor)s;
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}
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%(BasicExecDeclare)s
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};
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}};
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def template NeonX2RegImmOpDeclare {{
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template <class _Element>
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class %(class_name)s : public %(base_class)s
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{
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protected:
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typedef _Element Element;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _op2, _imm)
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{
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%(constructor)s;
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}
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%(BasicExecDeclare)s
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};
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}};
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def template NeonX1RegOpDeclare {{
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template <class _Element>
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class %(class_name)s : public %(base_class)s
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{
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protected:
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typedef _Element Element;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1)
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{
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%(constructor)s;
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}
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%(BasicExecDeclare)s
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};
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}};
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def template NeonX1RegImmOpDeclare {{
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template <class _Element>
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class %(class_name)s : public %(base_class)s
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{
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protected:
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typedef _Element Element;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _imm)
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{
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%(constructor)s;
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}
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%(BasicExecDeclare)s
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};
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}};
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def template NeonX1Reg2ImmOpDeclare {{
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template <class _Element>
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class %(class_name)s : public %(base_class)s
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{
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protected:
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typedef _Element Element;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1,
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uint64_t _imm2)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _imm1, _imm2)
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{
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%(constructor)s;
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}
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%(BasicExecDeclare)s
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};
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}};
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def template NeonX1RegImmOnlyOpDeclare {{
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template <class _Element>
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class %(class_name)s : public %(base_class)s
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{
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protected:
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typedef _Element Element;
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _imm)
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{
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%(constructor)s;
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}
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%(BasicExecDeclare)s
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};
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}};
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def template NeonXExecDeclare {{
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template
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Fault %(class_name)s<%(targs)s>::execute(
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CPU_EXEC_CONTEXT *, Trace::InstRecord *) const;
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}};
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def template NeonXEqualRegOpExecute {{
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template <class Element>
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Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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const unsigned rCount = %(r_count)d;
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const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
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const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element);
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union RegVect {
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FloatRegBits regs[rCount];
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Element elements[eCount];
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};
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union FullRegVect {
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FloatRegBits regs[4];
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Element elements[eCountFull];
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};
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%(code)s;
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if (fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template NeonXUnequalRegOpExecute {{
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template <class Element>
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Fault %(class_name)s<Element>::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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typedef typename bigger_type_t<Element>::type BigElement;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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const unsigned rCount = %(r_count)d;
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const unsigned eCount = rCount * sizeof(FloatRegBits) / sizeof(Element);
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const unsigned eCountFull = 4 * sizeof(FloatRegBits) / sizeof(Element);
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union RegVect {
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FloatRegBits regs[rCount];
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Element elements[eCount];
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BigElement bigElements[eCount / 2];
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};
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union BigRegVect {
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FloatRegBits regs[2 * rCount];
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BigElement elements[eCount];
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};
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union FullRegVect {
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FloatRegBits regs[4];
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Element elements[eCountFull];
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};
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%(code)s;
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if (fault == NoFault)
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{
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MicroNeonMemDeclare64 {{
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class %(class_name)s : public %(base_class)s
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{
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protected:
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// True if the base register is SP (used for SP alignment checking)
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bool baseIsSP;
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// Access size in bytes
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uint8_t accSize;
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// Vector element size (0 -> 8-bit, 1 -> 16-bit, 2 -> 32-bit,
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// 3 -> 64-bit)
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uint8_t eSize;
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public:
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%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _ura,
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uint32_t _imm, unsigned extraMemFlags, bool _baseIsSP,
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uint8_t _accSize, uint8_t _eSize)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
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_ura, _imm),
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baseIsSP(_baseIsSP), accSize(_accSize), eSize(_eSize)
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{
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memAccessFlags |= extraMemFlags;
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%(constructor)s;
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}
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template NeonLoadExecute64 {{
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Fault %(class_name)s::execute(
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CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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MemUnion memUnion;
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uint8_t *dataPtr = memUnion.bytes;
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if (fault == NoFault) {
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fault = xc->readMem(EA, dataPtr, accSize, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template NeonLoadInitiateAcc64 {{
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Fault %(class_name)s::initiateAcc(
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CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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MemUnion memUnion;
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uint8_t *dataPtr = memUnion.bytes;
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if (fault == NoFault) {
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fault = xc->readMem(EA, dataPtr, accSize, memAccessFlags);
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}
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return fault;
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}
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}};
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def template NeonLoadCompleteAcc64 {{
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Fault %(class_name)s::completeAcc(
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PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(mem_decl)s;
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%(op_decl)s;
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%(op_rd)s;
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MemUnion &memUnion = *(MemUnion *)pkt->getPtr<uint8_t>();
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template NeonStoreExecute64 {{
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Fault %(class_name)s::execute(
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CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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MemUnion memUnion;
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uint8_t *dataPtr = memUnion.bytes;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->writeMem(dataPtr, accSize, EA, memAccessFlags,
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NULL);
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template NeonStoreInitiateAcc64 {{
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Fault %(class_name)s::initiateAcc(
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CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(mem_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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MemUnion memUnion;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->writeMem(memUnion.bytes, accSize, EA, memAccessFlags,
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NULL);
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}
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return fault;
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}
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}};
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def template NeonStoreCompleteAcc64 {{
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Fault %(class_name)s::completeAcc(
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PacketPtr pkt, CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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return NoFault;
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}
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}};
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def template VMemMultDeclare64 {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd,
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RegIndex rm, uint8_t eSize, uint8_t dataSize,
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uint8_t numStructElems, uint8_t numRegs, bool wb);
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%(BasicExecPanic)s
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};
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}};
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def template VMemSingleDeclare64 {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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// Constructor
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%(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd,
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RegIndex rm, uint8_t eSize, uint8_t dataSize,
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uint8_t numStructElems, uint8_t index, bool wb,
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bool replicate = false);
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%(BasicExecPanic)s
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};
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}};
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|
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def template VMemMultConstructor64 {{
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%(class_name)s::%(class_name)s(
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ExtMachInst machInst, RegIndex rn, RegIndex vd, RegIndex rm,
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uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems,
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uint8_t _numRegs, bool _wb) :
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%(base_class)s(
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"%(mnemonic)s", machInst, %(op_class)s, rn, vd, rm,
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_eSize, _dataSize, _numStructElems, _numRegs, _wb)
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{
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%(constructor)s;
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}
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}};
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|
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def template VMemSingleConstructor64 {{
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%(class_name)s::%(class_name)s(
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ExtMachInst machInst, RegIndex rn, RegIndex vd, RegIndex rm,
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uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems,
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|
uint8_t _index, bool _wb, bool _replicate) :
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%(base_class)s(
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"%(mnemonic)s", machInst, %(op_class)s, rn, vd, rm,
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_eSize, _dataSize, _numStructElems, _index, _wb,
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_replicate)
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{
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%(constructor)s;
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}
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|
}};
|
|
|
|
def template MicroNeonMixDeclare64 {{
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|
class %(class_name)s : public %(base_class)s
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|
{
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|
public:
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|
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
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uint8_t _eSize, uint8_t _dataSize,
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uint8_t _numStructElems, uint8_t _numRegs,
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uint8_t _step) :
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%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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_dest, _op1, _eSize, _dataSize, _numStructElems,
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_numRegs, _step)
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|
{
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|
%(constructor)s;
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|
}
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%(BasicExecDeclare)s
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|
};
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|
}};
|
|
|
|
def template MicroNeonMixLaneDeclare64 {{
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|
class %(class_name)s : public %(base_class)s
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|
{
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|
public:
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|
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
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|
uint8_t _eSize, uint8_t _dataSize,
|
|
uint8_t _numStructElems, uint8_t _lane, uint8_t _step,
|
|
bool _replicate = false) :
|
|
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _op1, _eSize, _dataSize, _numStructElems,
|
|
_lane, _step, _replicate)
|
|
{
|
|
%(constructor)s;
|
|
}
|
|
|
|
%(BasicExecDeclare)s
|
|
};
|
|
}};
|
|
|
|
def template MicroNeonMixExecute64 {{
|
|
Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
|
|
Trace::InstRecord *traceData) const
|
|
{
|
|
Fault fault = NoFault;
|
|
uint64_t resTemp = 0;
|
|
resTemp = resTemp;
|
|
%(op_decl)s;
|
|
%(op_rd)s;
|
|
|
|
%(code)s;
|
|
if (fault == NoFault)
|
|
{
|
|
%(op_wb)s;
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
}};
|