fe27f937aa
This patch encompasses several interrelated and interdependent changes to the ISA generation step. The end goal is to reduce the size of the generated compilation units for instruction execution and decoding so that batch compilation can proceed with all CPUs active without exhausting physical memory. The ISA parser (src/arch/isa_parser.py) has been improved so that it can accept 'split [output_type];' directives at the top level of the grammar and 'split(output_type)' python calls within 'exec {{ ... }}' blocks. This has the effect of "splitting" the files into smaller compilation units. I use air-quotes around "splitting" because the files themselves are not split, but preprocessing directives are inserted to have the same effect. Architecturally, the ISA parser has had some changes in how it works. In general, it emits code sooner. It doesn't generate per-CPU files, and instead defers to the C preprocessor to create the duplicate copies for each CPU type. Likewise there are more files emitted and the C preprocessor does more substitution that used to be done by the ISA parser. Finally, the build system (SCons) needs to be able to cope with a dynamic list of source files coming out of the ISA parser. The changes to the SCons{cript,truct} files support this. In broad strokes, the targets requested on the command line are hidden from SCons until all the build dependencies are determined, otherwise it would try, realize it can't reach the goal, and terminate in failure. Since build steps (i.e. running the ISA parser) must be taken to determine the file list, several new build stages have been inserted at the very start of the build. First, the build dependencies from the ISA parser will be emitted to arch/$ISA/generated/inc.d, which is then read by a new SCons builder to finalize the dependencies. (Once inc.d exists, the ISA parser will not need to be run to complete this step.) Once the dependencies are known, the 'Environments' are made by the makeEnv() function. This function used to be called before the build began but now happens during the build. It is easy to see that this step is quite slow; this is a known issue and it's important to realize that it was already slow, but there was no obvious cause to attribute it to since nothing was displayed to the terminal. Since new steps that used to be performed serially are now in a potentially-parallel build phase, the pathname handling in the SCons scripts has been tightened up to deal with chdir() race conditions. In general, pathnames are computed earlier and more likely to be stored, passed around, and processed as absolute paths rather than relative paths. In the end, some of these issues had to be fixed by inserting serializing dependencies in the build. Minor note: For the null ISA, we just provide a dummy inc.d so SCons is never compelled to try to generate it. While it seems slightly wrong to have anything in src/arch/*/generated (i.e. a non-generated 'generated' file), it's by far the simplest solution.
478 lines
14 KiB
C++
478 lines
14 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// Alpha ISA description file.
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//
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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// Output include file directives.
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//
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output header {{
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#include <iomanip>
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#include <iostream>
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#include <sstream>
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#include "arch/alpha/faults.hh"
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#include "arch/alpha/types.hh"
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#include "config/ss_compatible_fp.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh" // some constructors use MemReq flags
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}};
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output decoder {{
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#include <cmath>
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#include "arch/alpha/decoder.hh"
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#include "arch/alpha/registers.hh"
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#include "arch/alpha/regredir.hh"
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#include "base/loader/symtab.hh"
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#include "base/cprintf.hh"
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#include "base/fenv.hh"
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#include "config/ss_compatible_fp.hh"
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#include "cpu/thread_context.hh" // for Jump::branchTarget()
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#include "mem/packet.hh"
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#include "sim/full_system.hh"
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using namespace AlphaISA;
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}};
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output exec {{
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#include <cmath>
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#include "arch/alpha/decoder.hh"
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#include "arch/alpha/registers.hh"
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#include "arch/alpha/regredir.hh"
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#include "arch/generic/memhelpers.hh"
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#include "base/cp_annotate.hh"
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#include "base/fenv.hh"
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#include "config/ss_compatible_fp.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/full_system.hh"
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#include "sim/pseudo_inst.hh"
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#include "sim/sim_exit.hh"
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using namespace AlphaISA;
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Namespace statement. Everything below this line will be in the
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// AlphaISAInst namespace.
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//
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namespace AlphaISA;
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////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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// Universal (format-independent) fields
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def bitfield PALMODE <32:32>;
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def bitfield OPCODE <31:26>;
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def bitfield RA <25:21>;
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def bitfield RB <20:16>;
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// Memory format
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def signed bitfield MEMDISP <15: 0>; // displacement
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def bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)
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// Memory-format jumps
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def bitfield JMPFUNC <15:14>; // function code (disp<15:14>)
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def bitfield JMPHINT <13: 0>; // tgt Icache idx hint (disp<13:0>)
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// Branch format
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def signed bitfield BRDISP <20: 0>; // displacement
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// Integer operate format(s>;
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def bitfield INTIMM <20:13>; // integer immediate (literal)
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def bitfield IMM <12:12>; // immediate flag
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def bitfield INTFUNC <11: 5>; // function code
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def bitfield RC < 4: 0>; // dest reg
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// Floating-point operate format
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def bitfield FA <25:21>;
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def bitfield FB <20:16>;
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def bitfield FP_FULLFUNC <15: 5>; // complete function code
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def bitfield FP_TRAPMODE <15:13>; // trapping mode
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def bitfield FP_ROUNDMODE <12:11>; // rounding mode
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def bitfield FP_TYPEFUNC <10: 5>; // type+func: handiest for decoding
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def bitfield FP_SRCTYPE <10: 9>; // source reg type
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def bitfield FP_SHORTFUNC < 8: 5>; // short function code
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def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func code
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def bitfield FC < 4: 0>; // dest reg
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// PALcode format
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def bitfield PALFUNC <25: 0>; // function code
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// EV5 PAL instructions:
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// HW_LD/HW_ST
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def bitfield HW_LDST_PHYS <15>; // address is physical
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def bitfield HW_LDST_ALT <14>; // use ALT_MODE IPR
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def bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write acc
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def bitfield HW_LDST_QUAD <12>; // size: 0=32b, 1=64b
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def bitfield HW_LDST_VPTE <11>; // HW_LD only: is PTE fetch
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def bitfield HW_LDST_LOCK <10>; // HW_LD only: is load locked
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def bitfield HW_LDST_COND <10>; // HW_ST only: is store conditional
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def signed bitfield HW_LDST_DISP <9:0>; // signed displacement
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// HW_REI
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def bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingk
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def bitfield HW_REI_MBZ <13: 0>; // must be zero
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// HW_MTPR/MW_MFPR
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def bitfield HW_IPR_IDX <15:0>; // IPR index
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// M5 instructions
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def bitfield M5FUNC <7:0>;
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def operand_types {{
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'sb' : 'int8_t',
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'ub' : 'uint8_t',
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'sw' : 'int16_t',
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'uw' : 'uint16_t',
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'sl' : 'int32_t',
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'ul' : 'uint32_t',
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'sq' : 'int64_t',
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'uq' : 'uint64_t',
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'sf' : 'float',
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'df' : 'double'
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}};
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def operands {{
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# Int regs default to unsigned, but code should not count on this.
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# For clarity, descriptions that depend on unsigned behavior should
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# explicitly specify '_uq'.
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'Ra': ('IntReg', 'uq', 'PALMODE ? reg_redir[RA] : RA',
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'IsInteger', 1),
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'Rb': ('IntReg', 'uq', 'PALMODE ? reg_redir[RB] : RB',
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'IsInteger', 2),
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'Rc': ('IntReg', 'uq', 'PALMODE ? reg_redir[RC] : RC',
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'IsInteger', 3),
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'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
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'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
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'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
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'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
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'PC': ('PCState', 'uq', 'pc', ( None, None, 'IsControl' ), 4),
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'NPC': ('PCState', 'uq', 'npc', ( None, None, 'IsControl' ), 4),
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'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1),
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'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1),
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'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1),
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# The next two are hacks for non-full-system call-pal emulation
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'R0': ('IntReg', 'uq', '0', None, 1),
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'R16': ('IntReg', 'uq', '16', None, 1),
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'R17': ('IntReg', 'uq', '17', None, 1),
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'R18': ('IntReg', 'uq', '18', None, 1)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Basic instruction classes/templates/formats etc.
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//
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output header {{
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// uncomment the following to get SimpleScalar-compatible disassembly
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// (useful for diffing output traces).
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// #define SS_COMPATIBLE_DISASSEMBLY
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/**
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* Base class for all Alpha static instructions.
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*/
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class AlphaStaticInst : public StaticInst
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{
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protected:
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/// Make AlphaISA register dependence tags directly visible in
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/// this class and derived classes. Maybe these should really
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/// live here and not in the AlphaISA namespace.
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enum DependenceTags {
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FP_Reg_Base = AlphaISA::FP_Reg_Base
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};
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/// Constructor.
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AlphaStaticInst(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: StaticInst(mnem, _machInst, __opClass)
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{
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}
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/// Print a register name for disassembly given the unique
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/// dependence tag number (FP or int).
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void printReg(std::ostream &os, int reg) const;
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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void
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advancePC(AlphaISA::PCState &pcState) const
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{
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pcState.advance();
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}
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};
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}};
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output decoder {{
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void
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AlphaStaticInst::printReg(std::ostream &os, int reg) const
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{
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if (reg < FP_Reg_Base) {
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ccprintf(os, "r%d", reg);
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}
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else {
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ccprintf(os, "f%d", reg - FP_Reg_Base);
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}
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}
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std::string
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AlphaStaticInst::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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}
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if (_numSrcRegs > 1) {
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if (_numDestRegs > 0) {
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if (_numSrcRegs > 0)
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ss << ",";
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printReg(ss, _destRegIdx[0]);
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}
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return ss.str();
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}
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}};
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// Declarations for execute() methods.
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def template BasicExecDeclare {{
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Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
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}};
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// Basic instruction class declaration template.
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def template BasicDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst);
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%(BasicExecDeclare)s
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};
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}};
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// Basic instruction class constructor template.
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def template BasicConstructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
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{
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%(constructor)s;
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}
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}};
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// Basic instruction class execute method template.
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def template BasicExecute {{
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Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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// Basic decode template.
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def template BasicDecode {{
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return new %(class_name)s(machInst);
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}};
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// Basic decode template, passing mnemonic in as string arg to constructor.
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def template BasicDecodeWithMnemonic {{
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return new %(class_name)s("%(mnemonic)s", machInst);
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}};
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// The most basic instruction format... used only for a few misc. insts
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def format BasicOperate(code, *flags) {{
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iop = InstObjParams(name, Name, 'AlphaStaticInst', code, flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// Nop
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//
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output header {{
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/**
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* Static instruction class for no-ops. This is a leaf class.
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*/
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class Nop : public AlphaStaticInst
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{
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/// Disassembly of original instruction.
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const std::string originalDisassembly;
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public:
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/// Constructor
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Nop(const std::string _originalDisassembly, ExtMachInst _machInst)
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: AlphaStaticInst("nop", _machInst, No_OpClass),
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originalDisassembly(_originalDisassembly)
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{
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flags[IsNop] = true;
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}
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~Nop() { }
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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%(BasicExecDeclare)s
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};
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/// Helper function for decoding nops. Substitute Nop object
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/// for original inst passed in as arg (and delete latter).
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static inline
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AlphaStaticInst *
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makeNop(AlphaStaticInst *inst)
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{
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AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
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delete inst;
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return nop;
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}
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}};
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output decoder {{
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std::string Nop::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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return originalDisassembly;
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#else
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return csprintf("%-10s (%s)", "nop", originalDisassembly);
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#endif
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}
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}};
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output exec {{
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Fault
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Nop::execute(CPU_EXEC_CONTEXT *, Trace::InstRecord *) const
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{
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return NoFault;
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}
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}};
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// integer & FP operate instructions use Rc as dest, so check for
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// Rc == 31 to detect nops
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def template OperateNopCheckDecode {{
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{
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AlphaStaticInst *i = new %(class_name)s(machInst);
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if (RC == 31) {
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i = makeNop(i);
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}
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return i;
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}
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}};
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// Like BasicOperate format, but generates NOP if RC/FC == 31
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def format BasicOperateWithNopCheck(code, *opt_args) {{
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iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_args)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = OperateNopCheckDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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// Integer instruction templates, formats, etc.
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##include "int.isa"
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// Floating-point instruction templates, formats, etc.
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##include "fp.isa"
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// Memory instruction templates, formats, etc.
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##include "mem.isa"
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// Branch/jump instruction templates, formats, etc.
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##include "branch.isa"
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// PAL instruction templates, formats, etc.
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##include "pal.isa"
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// Opcdec fault instruction templates, formats, etc.
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##include "opcdec.isa"
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// Unimplemented instruction templates, formats, etc.
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##include "unimp.isa"
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// Unknown instruction templates, formats, etc.
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##include "unknown.isa"
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// Execution utility functions
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##include "util.isa"
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// The actual decoder
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##include "decoder.isa"
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