780aa0a0eb
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere.
Still a functional access bug someplace I need to track down in timing mode.
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Fix corner case on assertion
tests/configs/memtest.py:
Updated memtester with uncacheable addresses and functional accesses
--HG--
extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
95 lines
3.1 KiB
Python
95 lines
3.1 KiB
Python
# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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import m5
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from m5.objects import *
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# --------------------
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# Base L1 Cache
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# ====================
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class L1(BaseCache):
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latency = 1
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block_size = 64
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mshrs = 12
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tgts_per_mshr = 8
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protocol = CoherenceProtocol(protocol='moesi')
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# ----------------------
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# Base L2 Cache
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# ----------------------
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class L2(BaseCache):
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block_size = 64
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latency = 10
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mshrs = 92
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tgts_per_mshr = 16
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write_buffers = 8
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#MAX CORES IS 8 with the fals sharing method
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nb_cores = 8
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cpus = [ MemTest(atomic=False, max_loads=1e12, percent_uncacheable=10, progress_interval=1000) for i in xrange(nb_cores) ]
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# system simulated
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system = System(cpu = cpus, funcmem = PhysicalMemory(),
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physmem = PhysicalMemory(), membus = Bus(clock="500GHz", width=16))
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# l2cache & bus
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system.toL2Bus = Bus(clock="500GHz", width=16)
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system.l2c = L2(size='64kB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.port
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# connect l2c to membus
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system.l2c.mem_side = system.membus.port
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which_port = 0
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# add L1 caches
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for cpu in cpus:
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cpu.l1c = L1(size = '32kB', assoc = 4)
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cpu.l1c.cpu_side = cpu.test
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cpu.l1c.mem_side = system.toL2Bus.port
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if which_port == 0:
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system.funcmem.port = cpu.functional
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which_port = 1
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else:
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system.funcmem.functional = cpu.functional
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# connect memory to membus
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system.physmem.port = system.membus.port
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# -----------------------
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# run simulation
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# -----------------------
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root = Root( system = system )
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root.system.mem_mode = 'timing'
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#root.trace.flags="Cache CachePort MemoryAccess"
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#root.trace.cycle=1
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