fda338f8d3
This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
702 lines
80 KiB
Plaintext
702 lines
80 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.076018 # Number of seconds simulated
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sim_ticks 76017712000 # Number of ticks simulated
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final_tick 76017712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 156722 # Simulator instruction rate (inst/s)
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host_op_rate 171594 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 69131199 # Simulator tick rate (ticks/s)
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host_mem_usage 238024 # Number of bytes of host memory used
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host_seconds 1099.62 # Real time elapsed on the host
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sim_insts 172333351 # Number of instructions simulated
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sim_ops 188686833 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 131968 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory
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system.physmem.bytes_read::total 244160 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 131968 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 131968 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 2062 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 3815 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 1736016 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1475867 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 3211883 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 1736016 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 1736016 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 1736016 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 1475867 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 3211883 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 400 # Number of system calls
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system.cpu.numCycles 152035425 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 96736502 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 76001405 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 6554044 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 46407824 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 44181263 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 4475583 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 89477 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 40615724 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 388321121 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 96736502 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 48656846 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 82257766 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 28468285 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 7213696 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 8844 # Number of stall cycles due to pending traps
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system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions
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system.cpu.fetch.CacheLines 37645633 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 1886253 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 151974828 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.798620 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.154172 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 69887899 45.99% 45.99% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 5501348 3.62% 49.61% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 10684945 7.03% 56.64% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 10435662 6.87% 63.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 8784636 5.78% 69.28% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 6836908 4.50% 73.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 6295744 4.14% 77.93% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 8337493 5.49% 83.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 25210193 16.59% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 151974828 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.636276 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.554149 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 46658969 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 5920762 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 76552571 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 1116980 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 21725546 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 14796577 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 162492 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 401466473 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 736417 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 21725546 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 52184597 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 714677 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 792157 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 72083528 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 4474323 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 378974639 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 320673 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 3580560 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 642268895 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 1614410837 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 1596806412 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 17604425 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 298092667 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 344176228 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 52668 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 52665 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 12854506 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 43974668 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 16894662 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 5833133 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 3767851 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 334792286 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 74530 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 252791404 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 896561 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 144952187 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 373840168 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 23248 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 151974828 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.663377 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.758905 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 58489364 38.49% 38.49% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 23011540 15.14% 53.63% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 25193746 16.58% 70.21% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 20486028 13.48% 83.69% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 12864515 8.46% 92.15% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 6577319 4.33% 96.48% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 4059001 2.67% 99.15% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 1110893 0.73% 99.88% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 182422 0.12% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 151974828 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 966666 37.58% 37.58% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 5596 0.22% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.80% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 136 0.01% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 25 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 1199658 46.64% 84.45% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 400010 15.55% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 197331718 78.06% 78.06% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 995910 0.39% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.46% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 33152 0.01% 78.47% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 164284 0.06% 78.53% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 255235 0.10% 78.63% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 76457 0.03% 78.66% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 467994 0.19% 78.85% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 206483 0.08% 78.93% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 71867 0.03% 78.96% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.96% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 38997717 15.43% 94.39% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 14190267 5.61% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 252791404 # Type of FU issued
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system.cpu.iq.rate 1.662714 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 2572091 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.010175 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 657257029 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 477588320 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 240562315 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 3769259 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 2249868 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 1852626 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 253473620 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 1889875 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 2022881 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 14119118 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 17181 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 19942 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 4243962 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 21725546 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 15871 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 334925114 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 838955 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 43974668 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 16894662 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 51980 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 19942 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 4105078 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 3945464 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 8050542 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 245797206 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 37379001 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 6994198 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 58298 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 51189045 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 54004994 # Number of branches executed
|
|
system.cpu.iew.exec_stores 13810044 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.616710 # Inst execution rate
|
|
system.cpu.iew.wb_sent 243546363 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 242414941 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 150055684 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 269132262 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.594464 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.557554 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 172347739 # The number of committed instructions
|
|
system.cpu.commit.commitCommittedOps 188701221 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 146223871 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 51282 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 6420079 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 130249283 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.448770 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.161298 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 60006705 46.07% 46.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 32087583 24.64% 70.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 13984606 10.74% 81.44% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 7660285 5.88% 87.32% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 4414959 3.39% 90.71% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1331514 1.02% 91.74% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1740633 1.34% 93.07% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 1281617 0.98% 94.06% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 7741381 5.94% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 130249283 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 172347739 # Number of instructions committed
|
|
system.cpu.commit.committedOps 188701221 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 42506250 # Number of memory references committed
|
|
system.cpu.commit.loads 29855550 # Number of loads committed
|
|
system.cpu.commit.membars 22408 # Number of memory barriers committed
|
|
system.cpu.commit.branches 40287748 # Number of branches committed
|
|
system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 150130481 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1848934 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 7741381 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 457427793 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 691694403 # The number of ROB writes
|
|
system.cpu.timesIdled 1790 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 60597 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 172333351 # Number of Instructions Simulated
|
|
system.cpu.committedOps 188686833 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 172333351 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.882217 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.882217 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.133508 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.133508 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 1091781968 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 388588148 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 2914249 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2512479 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 474590594 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 832168 # number of misc regfile writes
|
|
system.cpu.icache.replacements 2661 # number of replacements
|
|
system.cpu.icache.tagsinuse 1361.223505 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 37640447 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 4399 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 8556.591725 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1361.223505 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.664660 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.664660 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 37640447 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 37640447 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 37640447 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 37640447 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 37640447 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 37640447 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 5186 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 5186 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 5186 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 5186 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 5186 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 5186 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 114498500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 114498500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 114498500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 114498500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 114498500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 114498500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 37645633 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 37645633 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 37645633 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 37645633 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 37645633 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 37645633 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000138 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000138 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000138 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000138 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000138 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000138 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22078.384111 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 22078.384111 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 22078.384111 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 22078.384111 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 22078.384111 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 22078.384111 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 786 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 786 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 786 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 786 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 786 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4400 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 4400 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 4400 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 4400 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80222500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 80222500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80222500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 80222500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80222500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 80222500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18232.386364 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18232.386364 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18232.386364 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 18232.386364 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18232.386364 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 18232.386364 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 57 # number of replacements
|
|
system.cpu.dcache.tagsinuse 1415.756952 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 47292959 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 25371.759120 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 1415.756952 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.345644 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.345644 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 34877985 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 34877985 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 12356653 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 12356653 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 29848 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 29848 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 28473 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 28473 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 47234638 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 47234638 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 47234638 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 47234638 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1937 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1937 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 7634 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 7634 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 9571 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 9571 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 9571 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 9571 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 71164500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 71164500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 282690000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 282690000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 80500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 80500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 353854500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 353854500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 353854500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 353854500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 34879922 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 34879922 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29850 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 29850 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 28473 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 28473 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 47244209 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 47244209 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 47244209 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 47244209 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000617 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.000617 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.000203 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.000203 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.000203 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.000203 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36739.545689 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 36739.545689 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37030.390359 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 37030.390359 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 40250 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 40250 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 36971.528576 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 36971.528576 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 16 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1154 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 1154 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6553 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 6553 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 7707 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 7707 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 7707 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 7707 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 783 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1081 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 1081 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26652500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 26652500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38548000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 38548000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 65200500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 65200500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 65200500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 65200500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000087 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000087 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34038.952746 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34038.952746 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35659.574468 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35659.574468 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34978.809013 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 34978.809013 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34978.809013 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 34978.809013 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 1983.510934 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 2423 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 2749 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.881411 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 4.019168 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 1437.049576 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 542.442189 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.000123 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.043855 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.016554 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.060532 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2332 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 90 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2422 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 7 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 7 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2332 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2429 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2332 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2429 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2068 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 693 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 2761 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 1074 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 1074 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2068 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1767 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 3835 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2068 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1767 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 3835 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 72826000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25403500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 98229500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37378500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 37378500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 72826000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 62782000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 135608000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 72826000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 62782000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 135608000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 4400 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 783 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 5183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1081 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 1081 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 4400 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1864 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 6264 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 4400 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1864 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 6264 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.470000 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.885057 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.532703 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993525 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.993525 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.470000 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.947961 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.612229 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.470000 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.947961 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.612229 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35215.667311 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36657.287157 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35577.508149 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34803.072626 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34803.072626 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 35360.625815 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35215.667311 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 35530.277306 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 35360.625815 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2062 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 679 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 2741 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1074 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 1074 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2062 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 3815 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2062 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 3815 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66124000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22800500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 88924500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33930000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33930000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66124000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56730500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 122854500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66124000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56730500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 122854500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867178 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993525 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993525 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.609036 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.609036 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32067.895247 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33579.528719 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32442.356804 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31592.178771 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31592.178771 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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|
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---------- End Simulation Statistics ----------
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