fd8a4ff5a8
into zeep.pool:/z/saidi/work/m5.suncc --HG-- extra : convert_revision : 20f61a524a3b53fc0afcf53a24b5a1fe1d96f579
115 lines
4 KiB
C++
115 lines
4 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
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#define __ARCH_SPARC_ISA_TRAITS_HH__
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#include "arch/sparc/types.hh"
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#include "arch/sparc/sparc_traits.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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class StaticInstPtr;
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namespace BigEndianGuest {}
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namespace SparcISA
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{
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class RegFile;
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const int MachineBytes = 8;
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//This makes sure the big endian versions of certain functions are used.
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using namespace BigEndianGuest;
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// SPARC has a delay slot
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#define ISA_HAS_DELAY_SLOT 1
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// SPARC NOP (sethi %(hi(0), g0)
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const MachInst NoopMachInst = 0x01000000;
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// These enumerate all the registers for dependence tracking.
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enum DependenceTags {
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FP_Base_DepTag = 33,
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Ctrl_Base_DepTag = 97
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};
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// semantically meaningful register indices
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const int ZeroReg = 0; // architecturally meaningful
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// the rest of these depend on the ABI
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const int StackPointerReg = 14;
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const int ReturnAddressReg = 31; // post call, precall is 15
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const int ReturnValueReg = 8; // Post return, 24 is pre-return.
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const int FramePointerReg = 30;
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const int ArgumentReg0 = 8;
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const int ArgumentReg1 = 9;
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const int ArgumentReg2 = 10;
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const int ArgumentReg3 = 11;
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const int ArgumentReg4 = 12;
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const int ArgumentReg5 = 13;
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// Some OS syscall use a second register (o1) to return a second value
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const int SyscallPseudoReturnReg = ArgumentReg1;
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//XXX These numbers are bogus
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const int MaxInstSrcRegs = 8;
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const int MaxInstDestRegs = 9;
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//8K. This value is implmentation specific; and should probably
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//be somewhere else.
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const int LogVMPageSize = 13;
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const int VMPageSize = (1 << LogVMPageSize);
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//Why does both the previous set of constants and this one exist?
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const int PageShift = 13;
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const int PageBytes = 1ULL << PageShift;
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const int BranchPredAddrShiftAmt = 2;
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StaticInstPtr decodeInst(ExtMachInst);
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#if FULL_SYSTEM
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// I don't know what it's for, so I don't
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// know what SPARC's value should be
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// For loading... XXX This maybe could be USegEnd?? --ali
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const Addr LoadAddrMask = ULL(0xffffffffff);
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/////////// TLB Stuff ////////////
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const Addr StartVAddrHole = ULL(0x0000800000000000);
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const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
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const Addr VAddrAMask = ULL(0xFFFFFFFF);
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const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
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const Addr BytesInPageMask = ULL(0x1FFF);
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#endif
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}
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#endif // __ARCH_SPARC_ISA_TRAITS_HH__
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