397 lines
12 KiB
C++
397 lines
12 KiB
C++
/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* Redistribution and use of this software in source and binary forms,
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* with or without modification, are permitted provided that the
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* following conditions are met:
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*
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* The software must be used only for Non-Commercial Use which means any
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* use which is NOT directed to receiving any direct monetary
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* compensation for, or commercial advantage from such use. Illustrative
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* examples of non-commercial use are academic research, personal study,
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* teaching, education and corporate research & development.
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* Illustrative examples of commercial use are distributing products for
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* commercial advantage and providing services using the software for
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* commercial advantage.
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*
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* If you wish to use this software or functionality therein that may be
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* covered by patents for commercial use, please contact:
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* Director of Intellectual Property Licensing
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* Office of Strategy and Technology
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* Hewlett-Packard Company
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* 1501 Page Mill Road
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* Palo Alto, California 94304
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*
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* Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer. Redistributions
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* in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution. Neither the name of
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* the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission. No right of
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* sublicense is granted herewith. Derivatives of the software and
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* output created using the software may be prepared, but only for
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* Non-Commercial Uses. Derivatives of the software may be shared with
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* others provided: (i) the others agree to abide by the list of
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* conditions herein which includes the Non-Commercial Use restrictions;
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* and (ii) such Derivatives of the software include the above copyright
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* notice to acknowledge the contribution from this software where
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* applicable, this list of conditions and the disclaimer below.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_FAULTS_HH__
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#define __ARCH_X86_FAULTS_HH__
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#include "base/misc.hh"
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#include "sim/faults.hh"
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namespace X86ISA
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{
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// Base class for all x86 "faults" where faults is in the m5 sense
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class X86FaultBase : public FaultBase
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{
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protected:
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const char * faultName;
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const char * mnem;
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uint64_t errorCode;
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X86FaultBase(const char * _faultName, const char * _mnem,
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uint64_t _errorCode = 0) :
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faultName(_faultName), mnem(_mnem), errorCode(_errorCode)
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{
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}
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const char * name() const
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{
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return faultName;
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}
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virtual bool isBenign()
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{
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return true;
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}
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virtual const char * mnemonic() const
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{
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return mnem;
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}
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};
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// Base class for x86 faults which behave as if the underlying instruction
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// didn't happen.
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class X86Fault : public X86FaultBase
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{
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protected:
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X86Fault(const char * name, const char * mnem,
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uint64_t _errorCode = 0) :
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X86FaultBase(name, mnem, _errorCode)
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{}
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};
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// Base class for x86 traps which behave as if the underlying instruction
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// completed.
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class X86Trap : public X86FaultBase
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{
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protected:
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X86Trap(const char * name, const char * mnem,
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uint64_t _errorCode = 0) :
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X86FaultBase(name, mnem, _errorCode)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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#endif
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};
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// Base class for x86 aborts which seem to be catastrophic failures.
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class X86Abort : public X86FaultBase
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{
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protected:
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X86Abort(const char * name, const char * mnem,
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uint64_t _errorCode = 0) :
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X86FaultBase(name, mnem, _errorCode)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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#endif
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};
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// Base class for x86 interrupts.
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class X86Interrupt : public X86FaultBase
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{
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protected:
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X86Interrupt(const char * name, const char * mnem,
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uint64_t _errorCode = 0) :
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X86FaultBase(name, mnem, _errorCode)
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{}
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#if FULL_SYSTEM
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void invoke(ThreadContext * tc);
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#endif
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};
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class UnimpInstFault : public FaultBase
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{
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public:
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const char * name() const
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{
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return "unimplemented_micro";
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}
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void invoke(ThreadContext * tc)
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{
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panic("Unimplemented instruction!");
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}
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};
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static inline Fault genMachineCheckFault()
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{
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panic("Machine check fault not implemented in x86!\n");
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}
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// Below is a summary of the interrupt/exception information in the
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// architecture manuals.
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// Class | Type | vector | Cause | mnem
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//------------------------------------------------------------------------
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//Contrib Fault 0 Divide-by-Zero-Error #DE
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//Benign Either 1 Debug #DB
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//Benign Interrupt 2 Non-Maskable-Interrupt #NMI
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//Benign Trap 3 Breakpoint #BP
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//Benign Trap 4 Overflow #OF
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//Benign Fault 5 Bound-Range #BR
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//Benign Fault 6 Invalid-Opcode #UD
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//Benign Fault 7 Device-Not-Available #NM
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//Benign Abort 8 Double-Fault #DF
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// 9 Coprocessor-Segment-Overrun
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//Contrib Fault 10 Invalid-TSS #TS
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//Contrib Fault 11 Segment-Not-Present #NP
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//Contrib Fault 12 Stack #SS
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//Contrib Fault 13 General-Protection #GP
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//Either Fault 14 Page-Fault #PF
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// 15 Reserved
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//Benign Fault 16 x87 Floating-Point Exception Pending #MF
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//Benign Fault 17 Alignment-Check #AC
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//Benign Abort 18 Machine-Check #MC
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//Benign Fault 19 SIMD Floating-Point #XF
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// 20-29 Reserved
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//Contrib ? 30 Security Exception #SX
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// 31 Reserved
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//Benign Interrupt 0-255 External Interrupts #INTR
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//Benign Interrupt 0-255 Software Interrupts INTn
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class DivideByZero : public X86Fault
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{
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public:
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DivideByZero() :
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X86Fault("Divide-by-Zero-Error", "#DE")
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{}
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};
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class DebugException : public X86FaultBase
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{
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public:
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DebugException() :
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X86FaultBase("Debug", "#DB")
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{}
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};
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class NonMaskableInterrupt : public X86Interrupt
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{
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public:
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NonMaskableInterrupt() :
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X86Interrupt("Non-Maskable-Interrupt", "#NMI")
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{}
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};
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class Breakpoint : public X86Trap
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{
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public:
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Breakpoint() :
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X86Trap("Breakpoint", "#BP")
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{}
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};
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class OverflowTrap : public X86Trap
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{
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public:
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OverflowTrap() :
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X86Trap("Overflow", "#OF")
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{}
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};
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class BoundRange : public X86Fault
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{
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public:
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BoundRange() :
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X86Fault("Bound-Range", "#BR")
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{}
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};
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class InvalidOpcode : public X86Fault
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{
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public:
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InvalidOpcode() :
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X86Fault("Invalid-Opcode", "#UD")
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{}
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};
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class DeviceNotAvailable : public X86Fault
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{
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public:
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DeviceNotAvailable() :
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X86Fault("Device-Not-Available", "#NM")
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{}
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};
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class DoubleFault : public X86Abort
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{
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public:
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DoubleFault() :
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X86Abort("Double-Fault", "#DF")
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{}
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};
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class InvalidTSS : public X86Fault
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{
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public:
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InvalidTSS() :
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X86Fault("Invalid-TSS", "#TS")
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{}
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};
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class SegmentNotPresent : public X86Fault
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{
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public:
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SegmentNotPresent() :
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X86Fault("Segment-Not-Present", "#NP")
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{}
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};
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class StackFault : public X86Fault
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{
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public:
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StackFault() :
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X86Fault("Stack", "#SS")
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{}
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};
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class GeneralProtection : public X86Fault
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{
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public:
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GeneralProtection(uint64_t _errorCode) :
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X86Fault("General-Protection", "#GP", _errorCode)
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{}
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};
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class PageFault : public X86Fault
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{
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public:
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PageFault() :
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X86Fault("Page-Fault", "#PF")
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{}
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};
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class X87FpExceptionPending : public X86Fault
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{
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public:
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X87FpExceptionPending() :
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X86Fault("x87 Floating-Point Exception Pending", "#MF")
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{}
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};
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class AlignmentCheck : X86Fault
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{
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public:
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AlignmentCheck() :
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X86Fault("Alignment-Check", "#AC")
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{}
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};
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class MachineCheck : X86Abort
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{
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public:
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MachineCheck() :
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X86Abort("Machine-Check", "#MC")
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{}
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};
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class SIMDFloatingPointFault : X86Fault
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{
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public:
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SIMDFloatingPointFault() :
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X86Fault("SIMD Floating-Point", "#XF")
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{}
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};
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class SecurityException : X86FaultBase
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{
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public:
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SecurityException() :
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X86FaultBase("Security Exception", "#SX")
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{}
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};
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class ExternalInterrupt : X86Interrupt
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{
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public:
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ExternalInterrupt() :
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X86Interrupt("External Interrupt", "#INTR")
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{}
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};
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class SoftwareInterrupt : X86Interrupt
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{
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public:
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SoftwareInterrupt() :
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X86Interrupt("Software Interrupt", "INTn")
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{}
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};
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// These faults aren't part of the ISA definition. They trigger filling
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// the tlb on a miss and are to take the place of a hardware table walker.
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class FakeITLBFault : public X86Fault
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{
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protected:
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Addr vaddr;
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public:
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FakeITLBFault(Addr _vaddr) :
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X86Fault("fake instruction tlb fault", "itlb"),
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vaddr(_vaddr)
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{}
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void invoke(ThreadContext * tc);
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};
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class FakeDTLBFault : public X86Fault
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{
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protected:
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Addr vaddr;
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public:
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FakeDTLBFault(Addr _vaddr) :
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X86Fault("fake data tlb fault", "dtlb"),
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vaddr(_vaddr)
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{}
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void invoke(ThreadContext * tc);
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};
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};
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#endif // __ARCH_X86_FAULTS_HH__
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