gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
Nilay Vaish 9bc132e473 regressions: update stats due to branch predictor changes
The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.
2013-01-24 12:29:00 -06:00

220 lines
4.1 KiB
INI

[root]
type=Root
children=system
full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
boot_osflags=a
clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
branchPred=Null
checker=Null
clock=500
cpu_id=0
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=262144
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=X86TLB
children=walker
size=64
walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
clock=500
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=131072
system=system
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=X86LocalApic
clock=500
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
system=system
int_master=system.membus.slave[2]
int_slave=system.membus.master[2]
pio=system.membus.master[1]
[system.cpu.isa]
type=X86ISA
[system.cpu.itb]
type=X86TLB
children=walker
size=64
walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=X86PagetableWalker
clock=500
system=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
clock=500
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=2097152
system=system
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
clock=500
header_cycles=1
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=55300000000
system=system
uid=100
[system.membus]
type=CoherentBus
block_size=64
clock=1000
header_cycles=1
use_default_range=false
width=8
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
latency_var=0
null=false
range=0:268435455
zero=false
port=system.membus.master[0]