23bbec6a34
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision : d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
36 lines
1.2 KiB
Plaintext
36 lines
1.2 KiB
Plaintext
def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'shw' : ('signed int', 16),
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'uhw' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sd' : ('signed int', 64),
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'ud' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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'qf' : ('float', 128)
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}};
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def operands {{
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'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
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'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
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'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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'Sa': ('IntReg', 'uw', 'SA', 'IsInteger', 4),
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'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
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'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
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'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
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'Mem': ('Mem', 'ud', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
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#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
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#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
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#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
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# The next two are hacks for non-full-system call-pal emulation
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#'R0': ('IntReg', 'uq', '0', None, 1),
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#'R16': ('IntReg', 'uq', '16', None, 1)
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}};
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