fc6879097b
During address translation instructions (such as AT S1E1R_Xt) the exception level can be different than the current exception level. This patch fixes how the TLB determines what EL to use during these instructions. Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f
418 lines
14 KiB
C++
418 lines
14 KiB
C++
/*
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* Copyright (c) 2010-2013, 2016 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_TLB_HH__
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#define __ARCH_ARM_TLB_HH__
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/pagetable.hh"
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#include "arch/arm/utility.hh"
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#include "arch/arm/vtophys.hh"
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#include "arch/generic/tlb.hh"
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#include "base/statistics.hh"
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#include "mem/request.hh"
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#include "params/ArmTLB.hh"
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#include "sim/probe/pmu.hh"
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class ThreadContext;
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namespace ArmISA {
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class TableWalker;
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class Stage2LookUp;
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class Stage2MMU;
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class TLB;
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class TlbTestInterface
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{
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public:
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TlbTestInterface() {}
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virtual ~TlbTestInterface() {}
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/**
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* Check if a TLB translation should be forced to fail.
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*
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* @param req Request requiring a translation.
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* @param is_priv Access from a privileged mode (i.e., not EL0)
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* @param mode Access type
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* @param domain Domain type
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*/
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virtual Fault translationCheck(RequestPtr req, bool is_priv,
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BaseTLB::Mode mode,
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TlbEntry::DomainType domain) = 0;
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/**
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* Check if a page table walker access should be forced to fail.
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*
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* @param pa Physical address the walker is accessing
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* @param size Walker access size
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* @param va Virtual address that initiated the walk
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* @param is_secure Access from secure state
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* @param is_priv Access from a privileged mode (i.e., not EL0)
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* @param mode Access type
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* @param domain Domain type
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* @param lookup_level Page table walker level
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*/
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virtual Fault walkCheck(Addr pa, Addr size, Addr va, bool is_secure,
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Addr is_priv, BaseTLB::Mode mode,
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TlbEntry::DomainType domain,
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LookupLevel lookup_level) = 0;
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};
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class TLB : public BaseTLB
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{
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public:
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enum ArmFlags {
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AlignmentMask = 0x7,
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AlignByte = 0x0,
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AlignHalfWord = 0x1,
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AlignWord = 0x2,
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AlignDoubleWord = 0x3,
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AlignQuadWord = 0x4,
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AlignOctWord = 0x5,
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AllowUnaligned = 0x8,
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// Priv code operating as if it wasn't
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UserMode = 0x10,
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// Because zero otherwise looks like a valid setting and may be used
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// accidentally, this bit must be non-zero to show it was used on
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// purpose.
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MustBeOne = 0x40
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};
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enum ArmTranslationType {
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NormalTran = 0,
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S1CTran = 0x1,
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HypMode = 0x2,
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// Secure code operating as if it wasn't (required by some Address
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// Translate operations)
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S1S2NsTran = 0x4,
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// Address translation instructions (eg AT S1E0R_Xt) need to be handled
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// in special ways during translation because they could need to act
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// like a different EL than the current EL. The following flags are
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// for these instructions
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S1E0Tran = 0x8,
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S1E1Tran = 0x10,
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S1E2Tran = 0x20,
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S1E3Tran = 0x40,
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S12E0Tran = 0x80,
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S12E1Tran = 0x100
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};
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protected:
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TlbEntry* table; // the Page Table
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int size; // TLB Size
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bool isStage2; // Indicates this TLB is part of the second stage MMU
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bool stage2Req; // Indicates whether a stage 2 lookup is also required
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uint64_t _attr; // Memory attributes for last accessed TLB entry
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bool directToStage2; // Indicates whether all translation requests should
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// be routed directly to the stage 2 TLB
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TableWalker *tableWalker;
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TLB *stage2Tlb;
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Stage2MMU *stage2Mmu;
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TlbTestInterface *test;
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// Access Stats
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mutable Stats::Scalar instHits;
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mutable Stats::Scalar instMisses;
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mutable Stats::Scalar readHits;
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mutable Stats::Scalar readMisses;
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mutable Stats::Scalar writeHits;
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mutable Stats::Scalar writeMisses;
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mutable Stats::Scalar inserts;
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mutable Stats::Scalar flushTlb;
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mutable Stats::Scalar flushTlbMva;
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mutable Stats::Scalar flushTlbMvaAsid;
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mutable Stats::Scalar flushTlbAsid;
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mutable Stats::Scalar flushedEntries;
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mutable Stats::Scalar alignFaults;
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mutable Stats::Scalar prefetchFaults;
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mutable Stats::Scalar domainFaults;
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mutable Stats::Scalar permsFaults;
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Stats::Formula readAccesses;
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Stats::Formula writeAccesses;
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Stats::Formula instAccesses;
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Stats::Formula hits;
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Stats::Formula misses;
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Stats::Formula accesses;
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/** PMU probe for TLB refills */
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ProbePoints::PMUUPtr ppRefills;
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int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
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public:
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TLB(const ArmTLBParams *p);
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TLB(const Params *p, int _size, TableWalker *_walker);
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/** Lookup an entry in the TLB
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* @param vpn virtual address
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* @param asn context id/address space id to use
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* @param vmid The virtual machine ID used for stage 2 translation
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* @param secure if the lookup is secure
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* @param hyp if the lookup is done from hyp mode
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* @param functional if the lookup should modify state
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* @param ignore_asn if on lookup asn should be ignored
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* @return pointer to TLB entry if it exists
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*/
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TlbEntry *lookup(Addr vpn, uint16_t asn, uint8_t vmid, bool hyp,
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bool secure, bool functional,
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bool ignore_asn, uint8_t target_el);
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virtual ~TLB();
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void takeOverFrom(BaseTLB *otlb) override;
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/// setup all the back pointers
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void init() override;
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void setTestInterface(SimObject *ti);
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TableWalker *getTableWalker() { return tableWalker; }
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void setMMU(Stage2MMU *m, MasterID master_id);
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int getsize() const { return size; }
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void insert(Addr vaddr, TlbEntry &pte);
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Fault getTE(TlbEntry **te, RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool timing, bool functional,
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bool is_secure, ArmTranslationType tranType);
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Fault getResultTe(TlbEntry **te, RequestPtr req, ThreadContext *tc,
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Mode mode, Translation *translation, bool timing,
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bool functional, TlbEntry *mergeTe);
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Fault checkPermissions(TlbEntry *te, RequestPtr req, Mode mode);
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Fault checkPermissions64(TlbEntry *te, RequestPtr req, Mode mode,
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ThreadContext *tc);
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/** Reset the entire TLB
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* @param secure_lookup if the operation affects the secure world
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*/
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void flushAllSecurity(bool secure_lookup, uint8_t target_el,
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bool ignore_el = false);
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/** Remove all entries in the non secure world, depending on whether they
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* were allocated in hyp mode or not
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* @param hyp if the opperation affects hyp mode
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*/
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void flushAllNs(bool hyp, uint8_t target_el, bool ignore_el = false);
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/** Reset the entire TLB. Used for CPU switching to prevent stale
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* translations after multiple switches
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*/
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void flushAll() override
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{
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flushAllSecurity(false, 0, true);
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flushAllSecurity(true, 0, true);
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}
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/** Remove any entries that match both a va and asn
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* @param mva virtual address to flush
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* @param asn contextid/asn to flush on match
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* @param secure_lookup if the operation affects the secure world
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*/
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void flushMvaAsid(Addr mva, uint64_t asn, bool secure_lookup,
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uint8_t target_el);
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/** Remove any entries that match the asn
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* @param asn contextid/asn to flush on match
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* @param secure_lookup if the operation affects the secure world
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*/
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void flushAsid(uint64_t asn, bool secure_lookup, uint8_t target_el);
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/** Remove all entries that match the va regardless of asn
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* @param mva address to flush from cache
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* @param secure_lookup if the operation affects the secure world
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* @param hyp if the operation affects hyp mode
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*/
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void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el);
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void printTlb() const;
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void demapPage(Addr vaddr, uint64_t asn) override
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{
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// needed for x86 only
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panic("demapPage() is not implemented.\n");
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}
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/**
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* Do a functional lookup on the TLB (for debugging)
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* and don't modify any internal state
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* @param tc thread context to get the context id from
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* @param vaddr virtual address to translate
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* @param pa returned physical address
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* @return if the translation was successful
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*/
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bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
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/**
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* Do a functional lookup on the TLB (for checker cpu) that
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* behaves like a normal lookup without modifying any page table state.
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*/
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Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode,
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ArmTranslationType tranType = NormalTran);
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/** Accessor functions for memory attributes for last accessed TLB entry
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*/
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void
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setAttr(uint64_t attr)
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{
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_attr = attr;
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}
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uint64_t
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getAttr() const
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{
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return _attr;
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}
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Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay,
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bool timing, ArmTranslationType tranType, bool functional = false);
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Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay, bool timing);
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode,
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ArmTranslationType tranType = NormalTran);
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Fault translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode,
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ArmTranslationType tranType = NormalTran);
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Fault translateComplete(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode, ArmTranslationType tranType,
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bool callFromS2);
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Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
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void drainResume() override;
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// Checkpointing
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void serialize(CheckpointOut &cp) const override;
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void unserialize(CheckpointIn &cp) override;
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void regStats() override;
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void regProbePoints() override;
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/**
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* Get the table walker master port. This is used for migrating
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* port connections during a CPU takeOverFrom() call. For
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* architectures that do not have a table walker, NULL is
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* returned, hence the use of a pointer rather than a
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* reference. For ARM this method will always return a valid port
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* pointer.
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*
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* @return A pointer to the walker master port
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*/
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BaseMasterPort* getMasterPort() override;
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// Caching misc register values here.
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// Writing to misc registers needs to invalidate them.
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// translateFunctional/translateSe/translateFs checks if they are
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// invalid and call updateMiscReg if necessary.
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protected:
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CPSR cpsr;
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bool aarch64;
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ExceptionLevel aarch64EL;
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SCTLR sctlr;
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SCR scr;
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bool isPriv;
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bool isSecure;
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bool isHyp;
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TTBCR ttbcr;
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uint16_t asid;
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uint8_t vmid;
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PRRR prrr;
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NMRR nmrr;
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HCR hcr;
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uint32_t dacr;
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bool miscRegValid;
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ContextID miscRegContext;
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ArmTranslationType curTranType;
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// Cached copies of system-level properties
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bool haveLPAE;
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bool haveVirtualization;
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bool haveLargeAsid64;
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void updateMiscReg(ThreadContext *tc,
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ArmTranslationType tranType = NormalTran);
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public:
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const Params *
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params() const
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{
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return dynamic_cast<const Params *>(_params);
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}
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inline void invalidateMiscReg() { miscRegValid = false; }
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private:
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/** Remove any entries that match both a va and asn
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* @param mva virtual address to flush
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* @param asn contextid/asn to flush on match
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* @param secure_lookup if the operation affects the secure world
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* @param hyp if the operation affects hyp mode
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* @param ignore_asn if the flush should ignore the asn
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*/
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void _flushMva(Addr mva, uint64_t asn, bool secure_lookup,
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bool hyp, bool ignore_asn, uint8_t target_el);
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bool checkELMatch(uint8_t target_el, uint8_t tentry_el, bool ignore_el);
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public: /* Testing */
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Fault testTranslation(RequestPtr req, Mode mode,
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TlbEntry::DomainType domain);
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Fault testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode,
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TlbEntry::DomainType domain,
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LookupLevel lookup_level);
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};
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} // namespace ArmISA
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#endif // __ARCH_ARM_TLB_HH__
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