882 lines
100 KiB
Plaintext
882 lines
100 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.625047 # Number of seconds simulated
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sim_ticks 625047295000 # Number of ticks simulated
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final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 94484 # Simulator instruction rate (inst/s)
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host_op_rate 128674 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 42659692 # Simulator tick rate (ticks/s)
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host_mem_usage 264788 # Number of bytes of host memory used
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host_seconds 14651.94 # Real time elapsed on the host
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sim_insts 1384370590 # Number of instructions simulated
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sim_ops 1885325342 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 30242880 # Number of bytes read from this memory
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system.physmem.bytes_read::total 30398336 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 155456 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 155456 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
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system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 2429 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 472545 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 474974 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 248711 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 48384947 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 48633657 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 248711 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 248711 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 6767923 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 6767923 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 6767923 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 248711 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 48384947 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 55401580 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 474974 # Total number of read requests seen
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system.physmem.writeReqs 66098 # Total number of write requests seen
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system.physmem.cpureqs 545412 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 30398336 # Total number of bytes read from memory
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system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 30398336 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 166 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 4340 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 29671 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 29693 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 29623 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 29543 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 29652 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 29628 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 29613 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 29731 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 29744 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 29771 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 29793 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 29855 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 29658 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 29603 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 29624 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 29606 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 4129 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 4141 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 4096 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 4102 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 4129 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 4105 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 4104 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 4141 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 4162 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 4162 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 4162 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 4159 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 4135 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 4135 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 4108 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 4128 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 625047219500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 474974 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
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system.physmem.readPktSize::8 0 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # categorize write packet sizes
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system.physmem.writePktSize::1 0 # categorize write packet sizes
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system.physmem.writePktSize::2 0 # categorize write packet sizes
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system.physmem.writePktSize::3 0 # categorize write packet sizes
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system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::5 0 # categorize write packet sizes
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system.physmem.writePktSize::6 66098 # categorize write packet sizes
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system.physmem.writePktSize::7 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
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system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::6 4340 # categorize neither packet sizes
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system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
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system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
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system.physmem.rdQLenPdf::0 407751 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 66647 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 302 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
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system.physmem.totQLat 3340611483 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 18115671483 # Sum of mem lat for all requests
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system.physmem.totBusLat 1899232000 # Total cycles spent in databus access
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system.physmem.totBankLat 12875828000 # Total cycles spent in bank access
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system.physmem.avgQLat 7035.71 # Average queueing delay per request
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system.physmem.avgBankLat 27117.97 # Average bank access latency per request
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system.physmem.avgBusLat 4000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 38153.68 # Average memory access latency
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system.physmem.avgRdBW 48.63 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 6.77 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 48.63 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 6.77 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 0.35 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.03 # Average read queue length over time
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system.physmem.avgWrQLen 17.44 # Average write queue length over time
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system.physmem.readRowHits 249146 # Number of row buffer hits during reads
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system.physmem.writeRowHits 48036 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes
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system.physmem.avgGap 1155201.56 # Average gap between requests
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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system.cpu.numCycles 1250094591 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 438808047 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 349805436 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 30625316 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 249957064 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 227370417 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 52357585 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2806128 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 279728002 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 600743262 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 158308312 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 133148695 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 11515 # Number of stall cycles due to pending traps
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system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR
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system.cpu.fetch.CacheLines 333206369 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 10414827 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1215386936 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.589820 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.189306 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 614688205 50.58% 50.58% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 42445352 3.49% 54.07% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 95116159 7.83% 61.89% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 55675580 4.58% 66.47% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 72776602 5.99% 72.46% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 42276531 3.48% 75.94% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 31131234 2.56% 78.50% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 31565180 2.60% 81.10% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 229712093 18.90% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 1215386936 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.351020 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 1.829826 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 402796361 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 106301870 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 561862491 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 16807396 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 127618818 # Number of cycles decode is squashing
|
|
system.cpu.decode.BranchResolved 44638184 # Number of times decode resolved a branch
|
|
system.cpu.decode.BranchMispred 12819 # Number of times decode detected a branch misprediction
|
|
system.cpu.decode.DecodedInsts 3046676123 # Number of instructions handled by decode
|
|
system.cpu.decode.SquashedInsts 27895 # Number of squashed instructions handled by decode
|
|
system.cpu.rename.SquashCycles 127618818 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 438124604 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 35349497 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 425259 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 541326873 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 72541885 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 2975830632 # Number of instructions processed by rename
|
|
system.cpu.rename.ROBFullEvents 70 # Number of times rename has blocked due to ROB full
|
|
system.cpu.rename.IQFullEvents 4806802 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.LSQFullEvents 56918075 # Number of times rename has blocked due to LSQ full
|
|
system.cpu.rename.RenamedOperands 2945274289 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 14167459331 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 13596684512 # Number of integer rename lookups
|
|
system.cpu.rename.fp_rename_lookups 570774819 # Number of floating rename lookups
|
|
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 952134199 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 23805 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 21281 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 197120926 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 972834043 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 492760757 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 36385181 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 42690468 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 2809386355 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 28039 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 2437787250 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 13304140 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 911537771 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 2374413817 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 6655 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 1215386936 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 2.005770 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.875210 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 379434397 31.22% 31.22% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 183109361 15.07% 46.29% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 202931100 16.70% 62.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 170113731 14.00% 76.98% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 132526126 10.90% 87.88% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 93839529 7.72% 95.60% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 37911750 3.12% 98.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 12465689 1.03% 99.75% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 3055253 0.25% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 1215386936 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 714674 0.82% 0.82% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 24388 0.03% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.84% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 55116913 62.89% 63.74% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 31779800 36.26% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 1108876695 45.49% 45.49% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 11224297 0.46% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.95% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 6876477 0.28% 46.29% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 5502220 0.23% 46.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.51% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 23416324 0.96% 47.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.47% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 838276108 34.39% 81.86% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 442239839 18.14% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 2437787250 # Type of FU issued
|
|
system.cpu.iq.rate 1.950082 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 87635775 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.035949 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 6069393440 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 3638225906 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 2254362609 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 122507911 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 82793715 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 56449336 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 2462106345 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 63316680 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 84343916 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 341446862 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 7743 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1429272 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 215765460 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 365 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 127618818 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 13752826 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1562574 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 2809426795 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 1398231 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 972834043 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 492760757 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 18053 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 1558945 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 2522 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 1429272 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 32529008 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 1513965 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 34042973 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2363631235 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 792642751 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 74156015 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 12401 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 1216279993 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 322475744 # Number of branches executed
|
|
system.cpu.iew.exec_stores 423637242 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.890762 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2336496726 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2310811945 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1347866502 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2524860722 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.848510 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.533838 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 924090552 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 30613261 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1087768118 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.733215 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.398367 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 447474994 41.14% 41.14% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 288616071 26.53% 67.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 95091930 8.74% 76.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 70192926 6.45% 82.86% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 46475898 4.27% 87.14% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 22197093 2.04% 89.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 15849951 1.46% 90.64% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 10985154 1.01% 91.64% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 90884101 8.36% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1087768118 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 908382478 # Number of memory references committed
|
|
system.cpu.commit.loads 631387181 # Number of loads committed
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
|
system.cpu.commit.branches 299634395 # Number of branches committed
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 90884101 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 3806292582 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 5746483501 # The number of ROB writes
|
|
system.cpu.timesIdled 353075 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 34707655 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.903006 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.903006 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.107413 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.107413 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 11775193288 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2227107160 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 68795849 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 49561296 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1363965830 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
|
|
system.cpu.icache.replacements 22468 # number of replacements
|
|
system.cpu.icache.tagsinuse 1641.255803 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 333171598 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 24150 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 13795.925383 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1641.255803 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.801394 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.801394 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 333175666 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 333175666 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 333175666 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 333175666 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 333175666 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 333175666 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 30702 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 30702 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 30702 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 30702 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 30702 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 30702 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 468488500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 468488500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 468488500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 468488500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 468488500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 468488500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 333206368 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 333206368 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 333206368 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 333206368 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 333206368 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 333206368 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000092 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.000092 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000092 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.000092 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000092 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.000092 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15259.217641 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 15259.217641 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 15259.217641 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 15259.217641 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 15259.217641 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 1109 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 28 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 39.607143 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2210 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 2210 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 2210 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 2210 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 2210 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 2210 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 28492 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 28492 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 28492 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 28492 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 28492 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 28492 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 377164000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 377164000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 377164000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 377164000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 377164000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 377164000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000086 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.000086 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000086 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.000086 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13237.540362 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13237.540362 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13237.540362 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 13237.540362 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 442192 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 32688.738823 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1109575 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 474940 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 2.336242 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 1295.493946 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 49.994068 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 31343.250808 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.039535 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001526 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.956520 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.997581 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 21719 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1058021 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1079740 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 96308 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 96308 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 6442 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 6442 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 21719 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1064463 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1086182 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 21719 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1064463 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1086182 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 2431 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 406497 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 408928 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4340 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 4340 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66075 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66075 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 2431 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 472572 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 475003 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 2431 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 472572 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 475003 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 126924500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25862108500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 25989033000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3246043000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3246043000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 126924500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 29108151500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 29235076000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 126924500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 29108151500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 29235076000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 24150 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1464518 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1488668 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 96308 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 96308 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4343 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 4343 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72517 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 72517 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 24150 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1537035 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1561185 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 24150 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1537035 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1561185 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.100663 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.277564 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.274694 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999309 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.999309 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911166 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.911166 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.100663 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.307457 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.304258 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.100663 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.307457 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.304258 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52210.818593 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 63621.892658 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 63554.055971 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49126.643965 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49126.643965 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 61547.139702 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52210.818593 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 61595.167509 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 61547.139702 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66098 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 29 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 29 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 29 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2429 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 406470 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 408899 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4340 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4340 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66075 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66075 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 2429 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 472545 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 474974 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 2429 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 472545 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 474974 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 96251295 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20717048717 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20813300012 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 43404340 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 43404340 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2393684509 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2393684509 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96251295 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23110733226 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 23206984521 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96251295 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23110733226 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 23206984521 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.277545 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.274674 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999309 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999309 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911166 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911166 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.304239 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.100580 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307439 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.304239 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39625.893372 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50968.210980 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50900.833732 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36226.780310 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36226.780310 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39625.893372 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48906.946907 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48859.483932 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1532939 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4094.623683 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 970042937 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1537035 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 631.113109 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 332181000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.623683 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999664 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 693909081 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 693909081 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 276100966 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 276100966 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 9999 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 9999 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 970010047 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 970010047 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 970010047 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 970010047 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1953320 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1953320 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 834712 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 834712 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 2788032 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 2788032 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 2788032 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 2788032 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 67394089000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 67394089000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 39986185470 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 39986185470 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 171500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 171500 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 107380274470 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 107380274470 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 107380274470 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 107380274470 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 695862401 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 695862401 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10002 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 10002 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 972798079 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 972798079 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 972798079 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 972798079 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002807 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002807 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003014 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.003014 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.002866 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.002866 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.002866 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.002866 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34502.328855 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 34502.328855 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47904.169905 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 47904.169905 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 57166.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 57166.666667 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 38514.720947 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 38514.720947 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 38514.720947 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 2182 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 795 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 56 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 88 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 38.964286 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 9.034091 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 96308 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 96308 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488800 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 488800 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 757854 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 757854 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1246654 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1246654 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1246654 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1246654 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464520 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1464520 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76858 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 76858 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1541378 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1541378 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1541378 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1541378 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37907812500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 37907812500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3481886500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3481886500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 41389699000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 41389699000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 41389699000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 41389699000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002105 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002105 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25884.120736 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25884.120736 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45302.850712 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45302.850712 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26852.400255 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26852.400255 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|