fbdeb60316
This patch changes how the cache determines if snoops should be forwarded from the memory side to the CPU side. Instead of having a parameter, the cache now looks at the port connected on the CPU side, and if it is a snooping port, then snoops are forwarded. Less error prone, and less parameters to worry about. The patch also tidies up the CPU classes to ensure that their I-side port is not snooping by removing overrides to the snoop request handler, such that snoop requests will panic via the default MasterPort implement
195 lines
6.2 KiB
Python
195 lines
6.2 KiB
Python
# Copyright (c) 2012 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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from m5.objects import *
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# Simple ALU Instructions have a latency of 1
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class O3_ARM_v7a_Simple_Int(FUDesc):
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opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
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count = 2
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# Complex ALU instructions have a variable latencies
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class O3_ARM_v7a_Complex_Int(FUDesc):
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opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
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OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
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OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
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count = 1
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# Floating point and SIMD instructions
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class O3_ARM_v7a_FP(FUDesc):
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opList = [ OpDesc(opClass='SimdAdd', opLat=4),
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OpDesc(opClass='SimdAddAcc', opLat=4),
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OpDesc(opClass='SimdAlu', opLat=4),
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OpDesc(opClass='SimdCmp', opLat=4),
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OpDesc(opClass='SimdCvt', opLat=3),
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OpDesc(opClass='SimdMisc', opLat=3),
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OpDesc(opClass='SimdMult',opLat=5),
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OpDesc(opClass='SimdMultAcc',opLat=5),
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OpDesc(opClass='SimdShift',opLat=3),
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OpDesc(opClass='SimdShiftAcc', opLat=3),
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OpDesc(opClass='SimdSqrt', opLat=9),
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OpDesc(opClass='SimdFloatAdd',opLat=5),
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OpDesc(opClass='SimdFloatAlu',opLat=5),
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OpDesc(opClass='SimdFloatCmp', opLat=3),
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OpDesc(opClass='SimdFloatCvt', opLat=3),
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OpDesc(opClass='SimdFloatDiv', opLat=3),
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OpDesc(opClass='SimdFloatMisc', opLat=3),
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OpDesc(opClass='SimdFloatMult', opLat=3),
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OpDesc(opClass='SimdFloatMultAcc',opLat=1),
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OpDesc(opClass='SimdFloatSqrt', opLat=9),
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OpDesc(opClass='FloatAdd', opLat=5),
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OpDesc(opClass='FloatCmp', opLat=5),
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OpDesc(opClass='FloatCvt', opLat=5),
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OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
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OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
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OpDesc(opClass='FloatMult', opLat=4) ]
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count = 2
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# Load/Store Units
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class O3_ARM_v7a_Load(FUDesc):
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opList = [ OpDesc(opClass='MemRead',opLat=2) ]
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count = 1
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class O3_ARM_v7a_Store(FUDesc):
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opList = [OpDesc(opClass='MemWrite',opLat=2) ]
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count = 1
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# Functional Units for this CPU
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class O3_ARM_v7a_FUP(FUPool):
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FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
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O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
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# Bi-Mode Branch Predictor
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class O3_ARM_v7a_BP(BiModeBP):
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globalPredictorSize = 8192
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globalCtrBits = 2
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choicePredictorSize = 8192
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choiceCtrBits = 2
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BTBEntries = 2048
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BTBTagSize = 18
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RASSize = 16
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instShiftAmt = 2
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class O3_ARM_v7a_3(DerivO3CPU):
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LQEntries = 16
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SQEntries = 16
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LSQDepCheckShift = 0
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LFSTSize = 1024
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SSITSize = 1024
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decodeToFetchDelay = 1
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renameToFetchDelay = 1
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iewToFetchDelay = 1
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commitToFetchDelay = 1
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renameToDecodeDelay = 1
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iewToDecodeDelay = 1
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commitToDecodeDelay = 1
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iewToRenameDelay = 1
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commitToRenameDelay = 1
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commitToIEWDelay = 1
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fetchWidth = 3
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fetchBufferSize = 16
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fetchToDecodeDelay = 3
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decodeWidth = 3
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decodeToRenameDelay = 2
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renameWidth = 3
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renameToIEWDelay = 1
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issueToExecuteDelay = 1
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dispatchWidth = 6
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issueWidth = 8
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wbWidth = 8
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fuPool = O3_ARM_v7a_FUP()
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iewToCommitDelay = 1
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renameToROBDelay = 1
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commitWidth = 8
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squashWidth = 8
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trapLatency = 13
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backComSize = 5
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forwardComSize = 5
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numPhysIntRegs = 128
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numPhysFloatRegs = 192
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numIQEntries = 32
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numROBEntries = 40
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switched_out = False
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branchPred = O3_ARM_v7a_BP()
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# Instruction Cache
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class O3_ARM_v7a_ICache(Cache):
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hit_latency = 1
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response_latency = 1
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mshrs = 2
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tgts_per_mshr = 8
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size = '32kB'
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assoc = 2
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is_read_only = True
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# Writeback clean lines as well
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writeback_clean = True
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# Data Cache
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class O3_ARM_v7a_DCache(Cache):
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hit_latency = 2
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response_latency = 2
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mshrs = 6
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tgts_per_mshr = 8
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size = '32kB'
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assoc = 2
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write_buffers = 16
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# Consider the L2 a victim cache also for clean lines
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writeback_clean = True
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# TLB Cache
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# Use a cache as a L2 TLB
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class O3_ARM_v7aWalkCache(Cache):
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hit_latency = 4
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response_latency = 4
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mshrs = 6
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tgts_per_mshr = 8
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size = '1kB'
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assoc = 8
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write_buffers = 16
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is_read_only = True
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# Writeback clean lines as well
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writeback_clean = True
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# L2 Cache
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class O3_ARM_v7aL2(Cache):
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hit_latency = 12
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response_latency = 12
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mshrs = 16
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tgts_per_mshr = 8
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size = '1MB'
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assoc = 16
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write_buffers = 8
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prefetch_on_access = True
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clusivity = 'mostly_excl'
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# Simple stride prefetcher
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prefetcher = StridePrefetcher(degree=8, latency = 1)
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tags = RandomRepl()
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