d30262d480
arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision : 8e354b4232b28c0264d98d333d55ef8b5a6589cc
52 lines
1.1 KiB
Plaintext
52 lines
1.1 KiB
Plaintext
////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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def bitfield OPCODE_HI <31:29>;
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def bitfield OPCODE_LO <28:26>;
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def bitfield FUNCTION_HI < 5: 3>;
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def bitfield FUNCTION_LO < 2: 0>;
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// Integer operate format
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def bitfield RT <20:16>;
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def bitfield RT_HI <20:19>;
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def bitfield RT_LO <18:16>;
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def bitfield RS <25:21>;
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def bitfield RS_HI <25:24>;
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def bitfield RS_LO <23:21>;
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def bitfield RD <15:11>;
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def bitfield INTIMM <15: 0>; // integer immediate (literal)
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// Floating-point operate format
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def bitfield FMT <25:21>;
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def bitfield FT <20:16>;
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def bitfield FS <15:11>;
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def bitfield FD <10:6>;
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def bitfield MOVCI <16:16>;
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def bitfield MOVCF <16:16>;
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def bitfield SRL <21:21>;
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def bitfield SRLV < 6: 6>;
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def bitfield SA <10: 6>;
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// Interrupts
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def bitfield SC < 5: 5>;
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// Branch format
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def bitfield OFFSET <15: 0>; // displacement
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// Memory-format jumps
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def bitfield JMPTARG <25: 0>;
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def bitfield JMPHINT <10: 6>;
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def bitfield SYSCALLCODE <25: 6>;
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def bitfield TRAPCODE <15:13>;
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// M5 instructions
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def bitfield M5FUNC <7:0>;
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