5f0f42f166
Doxyfile:
Turn on EXTRACT_ALL so we get full class hierarchy info.
base/range.hh:
cpu/o3/fetch.hh:
cpu/o3/rename_map.hh:
cpu/o3/rob.hh:
dev/ide_disk.cc:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.hh:
Fix doxygen issues.
--HG--
extra : convert_revision : 9e0e8d3510b35db201459b8a3211c5e6ad5f0bb4
130 lines
3.4 KiB
C++
130 lines
3.4 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Implementation of Tsunami platform.
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "cpu/intr_control.hh"
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#include "dev/simconsole.hh"
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#include "dev/ide_ctrl.hh"
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#include "dev/tsunami_cchip.hh"
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#include "dev/tsunami_pchip.hh"
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#include "dev/tsunami_io.hh"
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#include "dev/tsunami.hh"
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#include "dev/pciconfigall.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
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PciConfigAll *pci)
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: Platform(name, ic, pci), system(s)
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{
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// set the back pointer from the system to myself
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system->platform = this;
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for (int i = 0; i < Tsunami::Max_CPUs; i++)
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intr_sum_type[i] = 0;
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}
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Tick
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Tsunami::intrFrequency()
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{
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return io->frequency();
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}
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void
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Tsunami::postConsoleInt()
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{
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io->postPIC(0x10);
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}
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void
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Tsunami::clearConsoleInt()
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{
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io->clearPIC(0x10);
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}
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void
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Tsunami::postPciInt(int line)
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{
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cchip->postDRIR(line);
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}
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void
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Tsunami::clearPciInt(int line)
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{
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cchip->clearDRIR(line);
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}
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Addr
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Tsunami::pciToDma(Addr pciAddr) const
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{
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return pchip->translatePciToDma(pciAddr);
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}
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void
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Tsunami::serialize(std::ostream &os)
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{
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SERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
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}
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void
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Tsunami::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
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SimObjectParam<System *> system;
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SimObjectParam<IntrControl *> intrctrl;
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SimObjectParam<PciConfigAll *> pciconfig;
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END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
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INIT_PARAM(system, "system"),
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INIT_PARAM(intrctrl, "interrupt controller"),
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INIT_PARAM(pciconfig, "PCI configuration")
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END_INIT_SIM_OBJECT_PARAMS(Tsunami)
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CREATE_SIM_OBJECT(Tsunami)
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{
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return new Tsunami(getInstanceName(), system, intrctrl, pciconfig);
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}
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REGISTER_SIM_OBJECT("Tsunami", Tsunami)
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