48863a1a43
makes it easier to implement PCI device models.
dev/pcidev.cc:
default implementations for read/write and readBarX/writeBarX functions
--HG--
extra : convert_revision : bbe2e2a2a506e2dd94d98f8e0feaefef96380be9
427 lines
14 KiB
C++
427 lines
14 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* A single PCI device configuration space entry.
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*/
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#include <list>
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#include <sstream>
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#include <string>
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#include <vector>
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#include "base/inifile.hh"
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#include "base/misc.hh"
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#include "base/str.hh" // for to_number
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#include "base/trace.hh"
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#include "dev/pcidev.hh"
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#include "dev/pciconfigall.hh"
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#include "mem/bus/bus.hh"
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#include "mem/functional/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/param.hh"
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#include "sim/root.hh"
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#include "dev/tsunamireg.h"
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using namespace std;
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PciDev::PciDev(Params *p)
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: DmaDevice(p->name, p->plat), _params(p), plat(p->plat),
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configData(p->configData)
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{
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// copy the config data from the PciConfigData object
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if (configData) {
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memcpy(config.data, configData->config.data, sizeof(config.data));
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memcpy(BARSize, configData->BARSize, sizeof(BARSize));
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memcpy(BARAddrs, configData->BARAddrs, sizeof(BARAddrs));
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} else
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panic("NULL pointer to configuration data");
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// Setup pointer in config space to point to this entry
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if (p->configSpace->deviceExists(p->deviceNum, p->functionNum))
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panic("Two PCI devices occuping same dev: %#x func: %#x",
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p->deviceNum, p->functionNum);
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else
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p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
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}
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Fault
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PciDev::read(MemReqPtr &req, uint8_t *data)
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{ return No_Fault; }
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Fault
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PciDev::write(MemReqPtr &req, const uint8_t *data)
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{ return No_Fault; }
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Fault
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PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
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{ panic("not implemented"); }
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Fault
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PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
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{ panic("not implemented"); }
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void
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PciDev::readConfig(int offset, int size, uint8_t *data)
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{
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if (offset >= PCI_DEVICE_SPECIFIC)
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panic("Device specific PCI config space not implemented!\n");
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switch(size) {
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case sizeof(uint8_t):
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*data = config.data[offset];
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break;
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case sizeof(uint16_t):
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*(uint16_t*)data = *(uint16_t*)&config.data[offset];
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break;
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case sizeof(uint32_t):
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*(uint32_t*)data = *(uint32_t*)&config.data[offset];
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break;
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default:
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panic("Invalid PCI configuration read size!\n");
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}
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DPRINTF(PCIDEV,
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"read device: %#x function: %#x register: %#x %d bytes: data: %#x\n",
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params()->deviceNum, params()->functionNum, offset, size,
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*(uint32_t*)data);
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}
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void
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PciDev::writeConfig(int offset, int size, const uint8_t *data)
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{
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if (offset >= PCI_DEVICE_SPECIFIC)
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panic("Device specific PCI config space not implemented!\n");
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uint8_t &data8 = *(uint8_t*)data;
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uint16_t &data16 = *(uint16_t*)data;
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uint32_t &data32 = *(uint32_t*)data;
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DPRINTF(PCIDEV,
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"write device: %#x function: %#x reg: %#x size: %d data: %#x\n",
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params()->deviceNum, params()->functionNum, offset, size, data32);
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switch (size) {
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case sizeof(uint8_t): // 1-byte access
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switch (offset) {
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case PCI0_INTERRUPT_LINE:
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config.interruptLine = data8;
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case PCI_CACHE_LINE_SIZE:
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config.cacheLineSize = data8;
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case PCI_LATENCY_TIMER:
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config.latencyTimer = data8;
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break;
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/* Do nothing for these read-only registers */
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case PCI0_INTERRUPT_PIN:
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case PCI0_MINIMUM_GRANT:
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case PCI0_MAXIMUM_LATENCY:
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case PCI_CLASS_CODE:
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case PCI_REVISION_ID:
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break;
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default:
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panic("writing to a read only register");
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}
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break;
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case sizeof(uint16_t): // 2-byte access
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switch (offset) {
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case PCI_COMMAND:
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config.command = data16;
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case PCI_STATUS:
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config.status = data16;
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case PCI_CACHE_LINE_SIZE:
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config.cacheLineSize = data16;
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break;
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default:
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panic("writing to a read only register");
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}
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break;
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case sizeof(uint32_t): // 4-byte access
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switch (offset) {
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case PCI0_BASE_ADDR0:
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case PCI0_BASE_ADDR1:
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case PCI0_BASE_ADDR2:
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case PCI0_BASE_ADDR3:
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case PCI0_BASE_ADDR4:
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case PCI0_BASE_ADDR5:
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uint32_t barnum, bar_mask;
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Addr base_addr, base_size, space_base;
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barnum = BAR_NUMBER(offset);
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if (BAR_IO_SPACE(letoh(config.baseAddr[barnum]))) {
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bar_mask = BAR_IO_MASK;
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space_base = TSUNAMI_PCI0_IO;
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} else {
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bar_mask = BAR_MEM_MASK;
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space_base = TSUNAMI_PCI0_MEMORY;
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}
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// Writing 0xffffffff to a BAR tells the card to set the
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// value of the bar to size of memory it needs
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if (letoh(data32) == 0xffffffff) {
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// This is I/O Space, bottom two bits are read only
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config.baseAddr[barnum] = letoh(
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(~(BARSize[barnum] - 1) & ~bar_mask) |
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(letoh(config.baseAddr[barnum]) & bar_mask));
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} else {
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MemoryController *mmu = params()->mmu;
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config.baseAddr[barnum] = letoh(
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(letoh(data32) & ~bar_mask) |
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(letoh(config.baseAddr[barnum]) & bar_mask));
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if (letoh(config.baseAddr[barnum]) & ~bar_mask) {
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base_addr = (letoh(data32) & ~bar_mask) + space_base;
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base_size = BARSize[barnum];
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// It's never been set
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if (BARAddrs[barnum] == 0)
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mmu->add_child((FunctionalMemory *)this,
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RangeSize(base_addr, base_size));
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else
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mmu->update_child((FunctionalMemory *)this,
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RangeSize(BARAddrs[barnum], base_size),
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RangeSize(base_addr, base_size));
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BARAddrs[barnum] = base_addr;
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}
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}
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break;
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case PCI0_ROM_BASE_ADDR:
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if (letoh(data32) == 0xfffffffe)
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config.expansionROM = htole((uint32_t)0xffffffff);
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else
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config.expansionROM = data32;
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break;
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case PCI_COMMAND:
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// This could also clear some of the error bits in the Status
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// register. However they should never get set, so lets ignore
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// it for now
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config.command = data16;
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break;
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default:
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DPRINTF(PCIDEV, "Writing to a read only register");
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}
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break;
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default:
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panic("invalid access size");
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}
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}
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void
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PciDev::serialize(ostream &os)
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{
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SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
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SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
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SERIALIZE_ARRAY(config.data, sizeof(config.data) / sizeof(config.data[0]));
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}
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void
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PciDev::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
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UNSERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
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UNSERIALIZE_ARRAY(config.data,
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sizeof(config.data) / sizeof(config.data[0]));
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// Add the MMU mappings for the BARs
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for (int i=0; i < 6; i++) {
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if (BARAddrs[i] != 0)
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params()->mmu->add_child(this, RangeSize(BARAddrs[i], BARSize[i]));
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}
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}
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#ifndef DOXYGEN_SHOULD_SKIP_THIS
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
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Param<uint16_t> VendorID;
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Param<uint16_t> DeviceID;
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Param<uint16_t> Command;
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Param<uint16_t> Status;
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Param<uint8_t> Revision;
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Param<uint8_t> ProgIF;
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Param<uint8_t> SubClassCode;
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Param<uint8_t> ClassCode;
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Param<uint8_t> CacheLineSize;
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Param<uint8_t> LatencyTimer;
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Param<uint8_t> HeaderType;
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Param<uint8_t> BIST;
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Param<uint32_t> BAR0;
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Param<uint32_t> BAR1;
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Param<uint32_t> BAR2;
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Param<uint32_t> BAR3;
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Param<uint32_t> BAR4;
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Param<uint32_t> BAR5;
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Param<uint32_t> CardbusCIS;
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Param<uint16_t> SubsystemVendorID;
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Param<uint16_t> SubsystemID;
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Param<uint32_t> ExpansionROM;
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Param<uint8_t> InterruptLine;
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Param<uint8_t> InterruptPin;
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Param<uint8_t> MinimumGrant;
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Param<uint8_t> MaximumLatency;
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Param<uint32_t> BAR0Size;
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Param<uint32_t> BAR1Size;
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Param<uint32_t> BAR2Size;
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Param<uint32_t> BAR3Size;
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Param<uint32_t> BAR4Size;
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Param<uint32_t> BAR5Size;
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END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
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BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
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INIT_PARAM(VendorID, "Vendor ID"),
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INIT_PARAM(DeviceID, "Device ID"),
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INIT_PARAM_DFLT(Command, "Command Register", 0x00),
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INIT_PARAM_DFLT(Status, "Status Register", 0x00),
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INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
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INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
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INIT_PARAM(SubClassCode, "Sub-Class Code"),
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INIT_PARAM(ClassCode, "Class Code"),
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INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
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INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
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INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
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INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
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INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
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INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
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INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
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INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
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INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
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INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
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INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
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INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
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INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
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INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
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INIT_PARAM(InterruptLine, "Interrupt Line Register"),
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INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
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INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
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INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
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INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
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INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
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INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
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INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
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INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
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INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
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END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
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CREATE_SIM_OBJECT(PciConfigData)
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{
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PciConfigData *data = new PciConfigData(getInstanceName());
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data->config.vendor = htole(VendorID);
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data->config.device = htole(DeviceID);
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data->config.command = htole(Command);
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data->config.status = htole(Status);
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data->config.revision = htole(Revision);
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data->config.progIF = htole(ProgIF);
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data->config.subClassCode = htole(SubClassCode);
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data->config.classCode = htole(ClassCode);
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data->config.cacheLineSize = htole(CacheLineSize);
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data->config.latencyTimer = htole(LatencyTimer);
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data->config.headerType = htole(HeaderType);
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data->config.bist = htole(BIST);
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data->config.baseAddr0 = htole(BAR0);
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data->config.baseAddr1 = htole(BAR1);
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data->config.baseAddr2 = htole(BAR2);
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data->config.baseAddr3 = htole(BAR3);
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data->config.baseAddr4 = htole(BAR4);
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data->config.baseAddr5 = htole(BAR5);
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data->config.cardbusCIS = htole(CardbusCIS);
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data->config.subsystemVendorID = htole(SubsystemVendorID);
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data->config.subsystemID = htole(SubsystemVendorID);
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data->config.expansionROM = htole(ExpansionROM);
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data->config.interruptLine = htole(InterruptLine);
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data->config.interruptPin = htole(InterruptPin);
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data->config.minimumGrant = htole(MinimumGrant);
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data->config.maximumLatency = htole(MaximumLatency);
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data->BARSize[0] = BAR0Size;
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data->BARSize[1] = BAR1Size;
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data->BARSize[2] = BAR2Size;
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data->BARSize[3] = BAR3Size;
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data->BARSize[4] = BAR4Size;
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data->BARSize[5] = BAR5Size;
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return data;
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}
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REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
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#endif // DOXYGEN_SHOULD_SKIP_THIS
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