306 lines
12 KiB
Python
306 lines
12 KiB
Python
# Copyright (c) 2015 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ron Dreslinski
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# Andreas Hansson
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import optparse
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import sys
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import m5
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from m5.objects import *
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parser = optparse.OptionParser()
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parser.add_option("-a", "--atomic", action="store_true",
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help="Use atomic (non-timing) mode")
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parser.add_option("-b", "--blocking", action="store_true",
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help="Use blocking caches")
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parser.add_option("-m", "--maxtick", type="int", default=m5.MaxTick,
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metavar="T",
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help="Stop after T ticks")
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parser.add_option("-p", "--prefetchers", action="store_true",
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help="Use prefetchers")
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parser.add_option("-s", "--stridepref", action="store_true",
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help="Use strided prefetchers")
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# This example script has a lot in common with the memtest.py in that
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# it is designed to stress tests the memory system. However, this
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# script uses oblivious traffic generators to create the stimuli, and
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# couples them with memcheckers to verify that the data read matches
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# the allowed outcomes. Just like memtest.py, the traffic generators
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# and checkers are placed in a tree topology. At the bottom of the
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# tree is a shared memory, and then at each level a number of
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# generators and checkers are attached, along with a number of caches
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# that them selves fan out to subtrees of generators and caches. Thus,
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# it is possible to create a system with arbitrarily deep cache
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# hierarchies, sharing or no sharing of caches, and generators not
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# only at the L1s, but also at the L2s, L3s etc.
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#
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# The tree specification consists of two colon-separated lists of one
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# or more integers, one for the caches, and one for the
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# testers/generators. The first integer is the number of
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# caches/testers closest to main memory. Each cache then fans out to a
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# subtree. The last integer in the list is the number of
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# caches/testers associated with the uppermost level of memory. The
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# other integers (if any) specify the number of caches/testers
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# connected at each level of the crossbar hierarchy. The tester string
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# should have one element more than the cache string as there should
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# always be testers attached to the uppermost caches.
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#
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# Since this script tests actual sharing, there is also a possibility
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# to stress prefetching and the interaction between prefetchers and
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# caches. The traffic generators switch between random address streams
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# and linear address streams to ensure that the prefetchers will
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# trigger. By default prefetchers are off.
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parser.add_option("-c", "--caches", type="string", default="3:2",
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help="Colon-separated cache hierarchy specification, "
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"see script comments for details "
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"[default: %default]")
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parser.add_option("-t", "--testers", type="string", default="1:0:2",
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help="Colon-separated tester hierarchy specification, "
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"see script comments for details "
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"[default: %default]")
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parser.add_option("--sys-clock", action="store", type="string",
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default='1GHz',
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help = """Top-level clock for blocks running at system
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speed""")
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# Start by parsing the command line options and do some basic sanity
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# checking
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try:
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cachespec = [int(x) for x in options.caches.split(':')]
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testerspec = [int(x) for x in options.testers.split(':')]
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except:
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print "Error: Unable to parse caches or testers option"
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sys.exit(1)
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if len(cachespec) < 1:
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print "Error: Must have at least one level of caches"
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sys.exit(1)
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if len(cachespec) != len(testerspec) - 1:
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print "Error: Testers must have one element more than caches"
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sys.exit(1)
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if testerspec[-1] == 0:
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print "Error: Must have testers at the uppermost level"
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sys.exit(1)
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for t in testerspec:
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if t < 0:
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print "Error: Cannot have a negative number of testers"
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sys.exit(1)
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for c in cachespec:
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if c < 1:
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print "Error: Must have 1 or more caches at each level"
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sys.exit(1)
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# Determine the tester multiplier for each level as the string
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# elements are per subsystem and it fans out
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multiplier = [1]
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for c in cachespec:
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if c < 1:
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print "Error: Must have at least one cache per level"
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multiplier.append(multiplier[-1] * c)
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numtesters = 0
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for t, m in zip(testerspec, multiplier):
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numtesters += t * m
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# Define a prototype L1 cache that we scale for all successive levels
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proto_l1 = Cache(size = '32kB', assoc = 4,
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hit_latency = 1, response_latency = 1,
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tgts_per_mshr = 8)
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if options.blocking:
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proto_l1.mshrs = 1
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else:
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proto_l1.mshrs = 4
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if options.prefetchers:
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proto_l1.prefetcher = TaggedPrefetcher()
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elif options.stridepref:
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proto_l1.prefetcher = StridePrefetcher()
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cache_proto = [proto_l1]
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# Now add additional cache levels (if any) by scaling L1 params, the
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# first element is Ln, and the last element L1
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for scale in cachespec[:-1]:
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# Clone previous level and update params
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prev = cache_proto[0]
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next = prev()
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next.size = prev.size * scale
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next.hit_latency = prev.hit_latency * 10
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next.response_latency = prev.response_latency * 10
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next.assoc = prev.assoc * scale
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next.mshrs = prev.mshrs * scale
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cache_proto.insert(0, next)
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# Create a config to be used by all the traffic generators
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cfg_file_name = "configs/example/memcheck.cfg"
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cfg_file = open(cfg_file_name, 'w')
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# Three states, with random, linear and idle behaviours. The random
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# and linear states access memory in the range [0 : 16 Mbyte] with 8
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# byte accesses.
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cfg_file.write("STATE 0 10000000 RANDOM 65 0 16777216 8 50000 150000 0\n")
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cfg_file.write("STATE 1 10000000 LINEAR 65 0 16777216 8 50000 150000 0\n")
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cfg_file.write("STATE 2 10000000 IDLE\n")
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cfg_file.write("INIT 0\n")
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cfg_file.write("TRANSITION 0 1 0.5\n")
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cfg_file.write("TRANSITION 0 2 0.5\n")
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cfg_file.write("TRANSITION 1 0 0.5\n")
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cfg_file.write("TRANSITION 1 2 0.5\n")
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cfg_file.write("TRANSITION 2 0 0.5\n")
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cfg_file.write("TRANSITION 2 1 0.5\n")
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cfg_file.close()
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# Make a prototype for the tester to be used throughout
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proto_tester = TrafficGen(config_file = cfg_file_name)
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# Set up the system along with a DRAM controller
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system = System(physmem = DDR3_1600_x64())
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system.voltage_domain = VoltageDomain(voltage = '1V')
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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system.memchecker = MemChecker()
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# For each level, track the next subsys index to use
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next_subsys_index = [0] * (len(cachespec) + 1)
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# Recursive function to create a sub-tree of the cache and tester
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# hierarchy
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def make_cache_level(ncaches, prototypes, level, next_cache):
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global next_subsys_index, proto_l1, testerspec, proto_tester
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index = next_subsys_index[level]
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next_subsys_index[level] += 1
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# Create a subsystem to contain the crossbar and caches, and
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# any testers
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subsys = SubSystem()
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setattr(system, 'l%dsubsys%d' % (level, index), subsys)
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# The levels are indexing backwards through the list
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ntesters = testerspec[len(cachespec) - level]
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testers = [proto_tester() for i in xrange(ntesters)]
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checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
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for i in xrange(ntesters)]
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if ntesters:
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subsys.tester = testers
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subsys.checkers = checkers
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if level != 0:
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# Create a crossbar and add it to the subsystem, note that
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# we do this even with a single element on this level
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xbar = L2XBar(width = 32)
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subsys.xbar = xbar
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if next_cache:
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xbar.master = next_cache.cpu_side
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# Create and connect the caches, both the ones fanning out
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# to create the tree, and the ones used to connect testers
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# on this level
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tree_caches = [prototypes[0]() for i in xrange(ncaches[0])]
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tester_caches = [proto_l1() for i in xrange(ntesters)]
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subsys.cache = tester_caches + tree_caches
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for cache in tree_caches:
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cache.mem_side = xbar.slave
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make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
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for tester, checker, cache in zip(testers, checkers, tester_caches):
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tester.port = checker.slave
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checker.master = cache.cpu_side
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cache.mem_side = xbar.slave
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else:
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if not next_cache:
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print "Error: No next-level cache at top level"
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sys.exit(1)
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if ntesters > 1:
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# Create a crossbar and add it to the subsystem
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xbar = L2XBar(width = 32)
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subsys.xbar = xbar
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xbar.master = next_cache.cpu_side
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for tester, checker in zip(testers, checkers):
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tester.port = checker.slave
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checker.master = xbar.slave
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else:
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# Single tester
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testers[0].port = checkers[0].slave
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checkers[0].master = next_cache.cpu_side
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# Top level call to create the cache hierarchy, bottom up
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make_cache_level(cachespec, cache_proto, len(cachespec), None)
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# Connect the lowest level crossbar to the memory
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last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
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last_subsys.xbar.master = system.physmem.port
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last_subsys.xbar.point_of_coherency = True
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root = Root(full_system = False, system = system)
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if options.atomic:
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root.system.mem_mode = 'atomic'
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else:
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root.system.mem_mode = 'timing'
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# The system port is never used in the tester so merely connect it
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# to avoid problems
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root.system.system_port = last_subsys.xbar.slave
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# Instantiate configuration
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m5.instantiate()
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# Simulate until program terminates
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exit_event = m5.simulate(options.maxtick)
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print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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