Brad Beckmann 29c45ccd23 ruby: Reduced ruby latencies ... The previous slower ruby latencies created a mismatch between the faster M5 cpu models and the much slower ruby memory system. Specifically smp interrupts were much slower and infrequent, as well as cpus moving in and out of spin locks. The result was many cpus were idle for large periods of time. These changes fix the latency mismatch.		2010-08-20 11:46:12 -07:00
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Benchmarks.py	style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs	2008-09-10 14:26:15 -04:00
CacheConfig.py	configs: pull out cache configuration code from se.py and fs.py.	2010-02-25 10:13:40 -08:00
Caches.py	python: Move more code into m5.util allow SCons to use that code.	2009-09-22 15:24:16 -07:00
cpu2000.py	ARM: fix sizes of structs for ARM Linux	2010-06-02 12:58:17 -05:00
FSConfig.py	config: fix assertion for x86 in FSConfig.py	2010-04-18 21:33:59 -07:00
Options.py	ruby: Reduced ruby latencies	2010-08-20 11:46:12 -07:00
Simulation.py	misc: add some AMD copyright notices	2010-08-17 05:49:05 -07:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00