Andreas Hansson 19a5b68db7 arch: Resurrect the NOISA build target and rename it NULL ... This patch makes it possible to once again build gem5 without any ISA. The main purpose is to enable work around the interconnect and memory system without having to build any CPU models or device models. The regress script is updated to include the NULL ISA target. Currently no regressions make use of it, but all the testers could (and perhaps should) transition to it. --HG-- rename : build_opts/NOISA => build_opts/NULL rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc		2013-09-04 13:22:57 -04:00
..
alpha	alpha: Move system virtProxy to Alpha only	2013-09-04 13:22:55 -04:00
arm	mem: Set the cache line size on a system level	2013-07-18 08:31:16 -04:00
generic	arch: Resurrect the NOISA build target and rename it NULL	2013-09-04 13:22:57 -04:00
mips	sim: Add the notion of clock domains to all ClockedObjects	2013-06-27 05:49:49 -04:00
null	arch: Resurrect the NOISA build target and rename it NULL	2013-09-04 13:22:57 -04:00
power	arch: Create a method to finalize physical addresses	2013-06-03 13:55:41 +02:00
sparc	arch: Create a method to finalize physical addresses	2013-06-03 13:55:41 +02:00
x86	x86: add tlb checkpointing	2013-08-07 14:51:17 -05:00
isa_parser.py	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	CPU: Merge the predecoder and decoder.	2012-05-26 13:44:46 -07:00