20e9a90edc
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
131 lines
3.4 KiB
C++
131 lines
3.4 KiB
C++
// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Integer operate instructions
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//
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//Outputs to decoder.hh
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output header {{
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#include <iostream>
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using namespace std;
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/**
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* Base class for integer operations.
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*/
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class IntOp : public MipsStaticInst
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{
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protected:
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/// Constructor
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IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class IntImmOp : public MipsStaticInst
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{
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protected:
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int32_t imm;
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/// Constructor
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IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
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MipsStaticInst(mnem, _machInst, __opClass),imm(INTIMM)
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{
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//If Bit 15 is 1 then Sign Extend
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int32_t temp = imm & 0x00008000;
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if (temp > 0 && mnemonic != "lui") {
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imm |= 0xFFFF0000;
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}
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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//Outputs to decoder.cc
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output decoder {{
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std::string IntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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// just print the first dest... if there's a second one,
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// it's generally implicit
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if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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}
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ss << ",";
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// just print the first two source regs... if there's
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// a third one, it's a read-modify-write dest (Rc),
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// e.g. for CMOVxx
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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}
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if (_numSrcRegs > 1) {
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ss << ",";
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printReg(ss, _srcRegIdx[1]);
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}
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return ss.str();
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}
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std::string IntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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ccprintf(ss, "%-10s ", mnemonic);
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if (_numDestRegs > 0) {
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printReg(ss, _destRegIdx[0]);
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}
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ss << ",";
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if (_numSrcRegs > 0) {
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printReg(ss, _srcRegIdx[0]);
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ss << ",";
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}
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if( mnemonic == "lui")
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ccprintf(ss, "%08p ", imm);
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else
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ss << (int) imm;
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return ss.str();
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}
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}};
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//Used by decoder.isa
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def format IntOp(code, *opt_flags) {{
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orig_code = code
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cblk = CodeBlock(code)
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# Figure out if we are creating a IntImmOp or a IntOp
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# by looking at the instruction name
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iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
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strlen = len(name)
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if name[strlen-1] == 'i' or name[strlen-2:] == 'iu':
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iop = InstObjParams(name, Name, 'IntImmOp', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = OperateNopCheckDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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