5b08e211ab
Mostly small differences in total ticks, but O3 stall causes shifted significantly. 30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8% slower.
900 lines
103 KiB
Text
900 lines
103 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 0.000027 # Number of seconds simulated
|
|
sim_ticks 26706500 # Number of ticks simulated
|
|
final_tick 26706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 22395 # Simulator instruction rate (inst/s)
|
|
host_op_rate 22394 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 41428038 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 228784 # Number of bytes of host memory used
|
|
host_seconds 0.64 # Real time elapsed on the host
|
|
sim_insts 14436 # Number of instructions simulated
|
|
sim_ops 14436 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory
|
|
system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
|
|
system.physmem.bw_read::cpu.inst 805197237 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 352273791 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 1157471028 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 805197237 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 805197237 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 805197237 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 352273791 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 1157471028 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 483 # Number of read requests accepted
|
|
system.physmem.writeReqs 0 # Number of write requests accepted
|
|
system.physmem.readBursts 483 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 30912 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 30912 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 102 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 29 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 51 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 24 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 19 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 32 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 35 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 4 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 1 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 0 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 57 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 31 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 61 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 36 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 26545500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 483 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 0 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 404.114286 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 265.832819 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 348.256092 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 22 31.43% 48.57% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 9 12.86% 61.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 3 4.29% 65.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 4 5.71% 71.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 3 4.29% 75.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 5 7.14% 82.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 2 2.86% 85.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 10 14.29% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation
|
|
system.physmem.totQLat 2649500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 11705750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2415000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 5485.51 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 24235.51 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 1157.47 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 1157.47 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 9.04 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 9.04 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 404 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
|
|
system.physmem.avgGap 54959.63 # Average gap between requests
|
|
system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 1553250 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 780000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 21299250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.membus.throughput 1157471028 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 400 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 400 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 83 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 83 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 966 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 966 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 30912 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 30912 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 603000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 4506000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 16.9 # Layer utilization (%)
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.branchPred.lookups 6723 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 4462 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 5029 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 2435 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 48.419169 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
|
|
system.cpu.workload.num_syscalls 18 # Number of system calls
|
|
system.cpu.numCycles 53414 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.fetch.icacheStallCycles 12428 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu.fetch.Insts 31151 # Number of instructions fetch has processed
|
|
system.cpu.fetch.Branches 6723 # Number of branches that fetch encountered
|
|
system.cpu.fetch.predictedBranches 2879 # Number of branches that fetch has predicted taken
|
|
system.cpu.fetch.Cycles 9139 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu.fetch.SquashCycles 3047 # Number of cycles fetch has spent squashing
|
|
system.cpu.fetch.BlockedCycles 8960 # Number of cycles fetch has spent blocked
|
|
system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps
|
|
system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched
|
|
system.cpu.fetch.IcacheSquashes 470 # Number of outstanding Icache misses that were squashed
|
|
system.cpu.fetch.rateDist::samples 33327 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::mean 0.934708 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::stdev 2.127415 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::0 24188 72.58% 72.58% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::1 4512 13.54% 86.12% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::2 474 1.42% 87.54% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::3 392 1.18% 88.71% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::4 683 2.05% 90.76% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::5 706 2.12% 92.88% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::6 235 0.71% 93.59% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::7 253 0.76% 94.35% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::8 1884 5.65% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.rateDist::total 33327 # Number of instructions fetched each cycle (Total)
|
|
system.cpu.fetch.branchRate 0.125866 # Number of branch fetches per cycle
|
|
system.cpu.fetch.rate 0.583199 # Number of inst fetches per cycle
|
|
system.cpu.decode.IdleCycles 12851 # Number of cycles decode is idle
|
|
system.cpu.decode.BlockedCycles 10052 # Number of cycles decode is blocked
|
|
system.cpu.decode.RunCycles 8399 # Number of cycles decode is running
|
|
system.cpu.decode.UnblockCycles 150 # Number of cycles decode is unblocking
|
|
system.cpu.decode.SquashCycles 1875 # Number of cycles decode is squashing
|
|
system.cpu.decode.DecodedInsts 29050 # Number of instructions handled by decode
|
|
system.cpu.rename.SquashCycles 1875 # Number of cycles rename is squashing
|
|
system.cpu.rename.IdleCycles 13476 # Number of cycles rename is idle
|
|
system.cpu.rename.BlockCycles 163 # Number of cycles rename is blocking
|
|
system.cpu.rename.serializeStallCycles 9186 # count of cycles rename stalled for serializing inst
|
|
system.cpu.rename.RunCycles 7977 # Number of cycles rename is running
|
|
system.cpu.rename.UnblockCycles 650 # Number of cycles rename is unblocking
|
|
system.cpu.rename.RenamedInsts 26689 # Number of instructions processed by rename
|
|
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
|
|
system.cpu.rename.SQFullEvents 339 # Number of times rename has blocked due to SQ full
|
|
system.cpu.rename.RenamedOperands 23975 # Number of destination operands rename has renamed
|
|
system.cpu.rename.RenameLookups 49504 # Number of register rename lookups that rename has made
|
|
system.cpu.rename.int_rename_lookups 40958 # Number of integer rename lookups
|
|
system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
|
|
system.cpu.rename.UndoneMaps 10156 # Number of HB maps that are undone due to squashing
|
|
system.cpu.rename.serializingInsts 691 # count of serializing insts renamed
|
|
system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed
|
|
system.cpu.rename.skidInsts 2667 # count of insts added to the skid buffer
|
|
system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu.memDep0.insertedStores 2291 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
|
|
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
|
|
system.cpu.iq.iqInstsAdded 22544 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ
|
|
system.cpu.iq.iqInstsIssued 21140 # Number of instructions issued
|
|
system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued
|
|
system.cpu.iq.iqSquashedInstsExamined 7925 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu.iq.iqSquashedOperandsExamined 5519 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed
|
|
system.cpu.iq.issued_per_cycle::samples 33327 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::mean 0.634321 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::stdev 1.264898 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::0 24173 72.53% 72.53% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::1 3454 10.36% 82.90% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::2 2274 6.82% 89.72% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::3 1733 5.20% 94.92% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::4 917 2.75% 97.67% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::5 470 1.41% 99.08% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::6 241 0.72% 99.80% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::7 45 0.14% 99.94% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu.iq.issued_per_cycle::total 33327 # Number of insts issued each cycle
|
|
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShift 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntAlu 15664 74.10% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemRead 3362 15.90% 90.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::MemWrite 2114 10.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu.iq.FU_type_0::total 21140 # Type of FU issued
|
|
system.cpu.iq.rate 0.395776 # Inst issue rate
|
|
system.cpu.iq.fu_busy_cnt 147 # FU busy when requested
|
|
system.cpu.iq.fu_busy_rate 0.006954 # FU busy rate (busy events/executed inst)
|
|
system.cpu.iq.int_inst_queue_reads 75851 # Number of integer instruction queue reads
|
|
system.cpu.iq.int_inst_queue_writes 31150 # Number of integer instruction queue writes
|
|
system.cpu.iq.int_inst_queue_wakeup_accesses 19533 # Number of integer instruction queue wakeup accesses
|
|
system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu.iq.int_alu_accesses 21287 # Number of integer alu accesses
|
|
system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 843 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1875 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 24333 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 388 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 2291 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 947 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 1211 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 20085 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 1055 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 1134 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 5227 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 4240 # Number of branches executed
|
|
system.cpu.iew.exec_stores 2025 # Number of stores executed
|
|
system.cpu.iew.exec_rate 0.376025 # Inst execution rate
|
|
system.cpu.iew.wb_sent 19760 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 19533 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 9201 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 11404 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.365691 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.806822 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitSquashedInsts 9073 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 31452 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.482068 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.184176 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 24226 77.03% 77.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 3950 12.56% 89.58% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 1330 4.23% 93.81% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 819 2.60% 96.42% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 349 1.11% 97.53% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 271 0.86% 98.39% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 322 1.02% 99.41% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 31452 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 15162 # Number of instructions committed
|
|
system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 3673 # Number of memory references committed
|
|
system.cpu.commit.loads 2225 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 3358 # Number of branches committed
|
|
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 187 # Number of function calls committed.
|
|
system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
|
|
system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 54747 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 50353 # The number of ROB writes
|
|
system.cpu.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 20087 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 14436 # Number of Instructions Simulated
|
|
system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.cpi 3.700055 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 3.700055 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.270266 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.270266 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 32058 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 17849 # number of integer regfile writes
|
|
system.cpu.misc_regfile_reads 6922 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 569 # number of misc regfile writes
|
|
system.cpu.toL2Bus.throughput 1162263868 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 31040 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 566000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 188.199882 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 14.414201 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 188.199882 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.091894 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.091894 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.165039 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 11098 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 11098 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 4872 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 508 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 31702750 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 31702750 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 31702750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 31702750 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 31702750 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 31702750 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094424 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.094424 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.094424 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.094424 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.094424 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.094424 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62406.988189 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 62406.988189 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 62406.988189 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 62406.988189 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 62406.988189 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22584000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 22584000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22584000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 22584000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22584000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 22584000 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062825 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.062825 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062825 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.062825 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66816.568047 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66816.568047 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66816.568047 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 66816.568047 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 222.048188 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.592876 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455312 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005725 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001051 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.006776 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012207 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 4363 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 4363 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 64 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 483 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22226000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4637250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 26863250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 6075250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 22226000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10712500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 32938500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 22226000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10712500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 32938500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994083 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66148.809524 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72457.031250 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.125000 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73195.783133 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73195.783133 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 68195.652174 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66148.809524 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72874.149660 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 68195.652174 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18000000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3851750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21851750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5060250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5060250 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18000000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 26912000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18000000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 26912000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.428571 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60183.593750 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54629.375000 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60966.867470 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60966.867470 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.428571 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60625.850340 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55718.426501 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.428571 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60625.850340 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55718.426501 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 99.055513 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 99.055513 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.024183 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.024183 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 9219 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 9219 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
|
|
system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
|
|
system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 3995 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 3995 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 3995 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 3995 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 535 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7969250 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 7969250 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 25782224 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 25782224 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 33751474 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 33751474 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 33751474 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 33751474 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63248.015873 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 63248.015873 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63037.222494 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 63037.222494 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 63086.867290 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 63086.867290 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 63086.867290 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 851 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.392857 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4701750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4701750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6159250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 6159250 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10861000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 10861000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10861000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10861000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74207.831325 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74207.831325 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73884.353741 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 73884.353741 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|