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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Steve Reinhardt 5b08e211ab stats: update for O3 changes 
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM.  At the other extreme, X86 70.twolf is 0.8%
slower.
2014-06-22 14:33:09 -07:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.525889 # Number of seconds simulated
sim_ticks 2525888859000 # Number of ticks simulated
final_tick 2525888859000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 55568 # Simulator instruction rate (inst/s)
host_op_rate 71500 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2327295647 # Simulator tick rate (ticks/s)
host_mem_usage 420424 # Number of bytes of host memory used
host_seconds 1085.33 # Real time elapsed on the host
sim_insts 60309513 # Number of instructions simulated
sim_ops 77601128 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 3072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9094168 # Number of bytes read from this memory
system.physmem.bytes_read::total 129432216 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 48 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142132 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15096846 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47324990 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 1216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 315631 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3600383 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51242245 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 315631 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 315631 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1498492 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1194064 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2692556 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1498492 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47324990 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 1216 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 315631 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4794447 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53934801 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15096846 # Number of read requests accepted
system.physmem.writeReqs 813159 # Number of write requests accepted
system.physmem.readBursts 15096846 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 961407104 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 4791040 # Total number of bytes read from write queue
system.physmem.bytesWritten 6818432 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 129432216 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 74860 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 706594 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4696 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 943526 # Per bank write bursts
system.physmem.perBankRdBursts::1 937990 # Per bank write bursts
system.physmem.perBankRdBursts::2 937469 # Per bank write bursts
system.physmem.perBankRdBursts::3 937431 # Per bank write bursts
system.physmem.perBankRdBursts::4 943079 # Per bank write bursts
system.physmem.perBankRdBursts::5 938170 # Per bank write bursts
system.physmem.perBankRdBursts::6 937203 # Per bank write bursts
system.physmem.perBankRdBursts::7 936910 # Per bank write bursts
system.physmem.perBankRdBursts::8 943866 # Per bank write bursts
system.physmem.perBankRdBursts::9 938107 # Per bank write bursts
system.physmem.perBankRdBursts::10 936563 # Per bank write bursts
system.physmem.perBankRdBursts::11 936045 # Per bank write bursts
system.physmem.perBankRdBursts::12 943886 # Per bank write bursts
system.physmem.perBankRdBursts::13 937531 # Per bank write bursts
system.physmem.perBankRdBursts::14 937186 # Per bank write bursts
system.physmem.perBankRdBursts::15 937024 # Per bank write bursts
system.physmem.perBankWrBursts::0 6617 # Per bank write bursts
system.physmem.perBankWrBursts::1 6376 # Per bank write bursts
system.physmem.perBankWrBursts::2 6529 # Per bank write bursts
system.physmem.perBankWrBursts::3 6558 # Per bank write bursts
system.physmem.perBankWrBursts::4 6459 # Per bank write bursts
system.physmem.perBankWrBursts::5 6705 # Per bank write bursts
system.physmem.perBankWrBursts::6 6711 # Per bank write bursts
system.physmem.perBankWrBursts::7 6649 # Per bank write bursts
system.physmem.perBankWrBursts::8 7036 # Per bank write bursts
system.physmem.perBankWrBursts::9 6794 # Per bank write bursts
system.physmem.perBankWrBursts::10 6454 # Per bank write bursts
system.physmem.perBankWrBursts::11 6111 # Per bank write bursts
system.physmem.perBankWrBursts::12 7073 # Per bank write bursts
system.physmem.perBankWrBursts::13 6679 # Per bank write bursts
system.physmem.perBankWrBursts::14 6963 # Per bank write bursts
system.physmem.perBankWrBursts::15 6824 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2525887732500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 38 # Read request sizes (log2)
system.physmem.readPktSize::3 14942208 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 154600 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 754018 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 59141 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1057329 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 995712 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 953847 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 1057444 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 956989 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1015779 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2635918 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 2545995 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 3318157 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 125455 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 108163 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 99319 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 95398 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 19431 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 18601 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 18316 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 110 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2592 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2806 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4314 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 6296 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 6465 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6388 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6736 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6476 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 6428 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 6463 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 6391 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 6379 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 6746 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6351 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6353 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6486 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 6262 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 995372 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 972.727318 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 907.205467 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 202.336600 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 22984 2.31% 2.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 19752 1.98% 4.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 8337 0.84% 5.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2265 0.23% 5.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2301 0.23% 5.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1840 0.18% 5.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 8587 0.86% 6.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 978 0.10% 6.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 928328 93.26% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 995372 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6241 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 2406.981894 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 114987.414706 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-524287 6237 99.94% 99.94% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6241 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6241 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.070662 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.017388 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.386394 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 3585 57.44% 57.44% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 32 0.51% 57.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 1616 25.89% 83.85% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 845 13.54% 97.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 54 0.87% 98.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 36 0.58% 98.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 33 0.53% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 31 0.50% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 9 0.14% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6241 # Writes before turning the bus around for reads
system.physmem.totQLat 389024977250 # Total ticks spent queuing
system.physmem.totMemAccLat 670687214750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 75109930000 # Total ticks spent in databus transfers
system.physmem.avgQLat 25897.04 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 44647.04 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 380.62 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.99 # Data bus utilization in percentage
system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.12 # Average write queue length when enqueuing
system.physmem.readRowHits 14042089 # Number of row buffer hits during reads
system.physmem.writeRowHits 91063 # Number of row buffer hits during writes
system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes
system.physmem.avgGap 158760.96 # Average gap between requests
system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 2186215098000 # Time in different power states
system.physmem.memoryStateTime::REF 84344780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 255323240750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 54884184 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16149487 # Transaction distribution
system.membus.trans_dist::ReadResp 16149487 # Transaction distribution
system.membus.trans_dist::WriteReq 763349 # Transaction distribution
system.membus.trans_dist::WriteResp 763349 # Transaction distribution
system.membus.trans_dist::Writeback 59141 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4696 # Transaction distribution
system.membus.trans_dist::ReadExReq 131431 # Transaction distribution
system.membus.trans_dist::ReadExResp 131431 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383042 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272651 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 34157067 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390450 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16695648 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19093686 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 138631350 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 138631350 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1486861000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3602500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks)
system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 17311099000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.7 # Layer utilization (%)
system.membus.respLayer1.occupancy 4710414902 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 36916757411 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.5 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.iobus.throughput 48271369 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16125555 # Transaction distribution
system.iobus.trans_dist::ReadResp 16125555 # Transaction distribution
system.iobus.trans_dist::WriteReq 8174 # Transaction distribution
system.iobus.trans_dist::WriteResp 8174 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 516 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1024 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2383042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 29884416 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 32267458 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1032 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2048 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390450 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119537664 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 121928114 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 121928114 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3972000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 516000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 518000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 14942208000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 37649719589 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 14910337 # Number of BP lookups
system.cpu.branchPred.condPredicted 11976867 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 705848 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 9580478 # Number of BTB lookups
system.cpu.branchPred.BTBHits 7742107 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 80.811281 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1408303 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 72648 # Number of incorrect RAS predictions.
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 14987595 # DTB read hits
system.cpu.checker.dtb.read_misses 7306 # DTB read misses
system.cpu.checker.dtb.write_hits 11227720 # DTB write hits
system.cpu.checker.dtb.write_misses 2191 # DTB write misses
system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.checker.dtb.flush_entries 3398 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.checker.dtb.read_accesses 14994901 # DTB read accesses
system.cpu.checker.dtb.write_accesses 11229911 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.dtb.hits 26215315 # DTB hits
system.cpu.checker.dtb.misses 9497 # DTB misses
system.cpu.checker.dtb.accesses 26224812 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.itb.inst_hits 61483491 # ITB inst hits
system.cpu.checker.itb.inst_misses 4473 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.checker.itb.flush_entries 2372 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
system.cpu.checker.itb.inst_accesses 61487964 # ITB inst accesses
system.cpu.checker.itb.hits 61483491 # DTB hits
system.cpu.checker.itb.misses 4473 # DTB misses
system.cpu.checker.itb.accesses 61487964 # DTB accesses
system.cpu.checker.numCycles 77886925 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 51097792 # DTB read hits
system.cpu.dtb.read_misses 64987 # DTB read misses
system.cpu.dtb.write_hits 11709971 # DTB write hits
system.cpu.dtb.write_misses 15921 # DTB write misses
system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3472 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 2569 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 428 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 51162779 # DTB read accesses
system.cpu.dtb.write_accesses 11725892 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 62807763 # DTB hits
system.cpu.dtb.misses 80908 # DTB misses
system.cpu.dtb.accesses 62888671 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 11575507 # ITB inst hits
system.cpu.itb.inst_misses 11335 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2514 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 2954 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 11586842 # ITB inst accesses
system.cpu.itb.hits 11575507 # DTB hits
system.cpu.itb.misses 11335 # DTB misses
system.cpu.itb.accesses 11586842 # DTB accesses
system.cpu.numCycles 476238509 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 29789702 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 91027179 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14910337 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 9150410 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 20302096 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 4754274 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 125108 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.BlockedCycles 93772455 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 2699 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 88682 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 2727734 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 553 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 11572027 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 712397 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 5390 # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples 150113292 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.756026 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.113644 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 129826802 86.49% 86.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 1312716 0.87% 87.36% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 1720953 1.15% 88.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 2304331 1.54% 90.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 2116294 1.41% 91.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 1112529 0.74% 92.19% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 2605432 1.74% 93.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 752346 0.50% 94.43% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 8361889 5.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 150113292 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.031309 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.191138 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 31268958 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 96222513 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 18495001 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 992442 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 3134378 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 1970530 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 172531 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 108153308 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 572201 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 3134378 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 32906794 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 14229038 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 56831984 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 17995352 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 25015746 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 103064055 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1610 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 17097046 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 19764397 # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents 2757051 # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents 1781 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 107250734 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 477314257 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 435890251 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10500 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 78727504 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 28523229 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1172187 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1078501 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 11007211 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 19896895 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 13369840 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 2003415 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2457274 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 95806828 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1986007 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 122955094 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 190842 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 19616274 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 49695395 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 503680 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 150113292 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.819082 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.543742 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 106692829 71.07% 71.07% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 13471343 8.97% 80.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 6554897 4.37% 84.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 5548193 3.70% 88.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 12665338 8.44% 96.55% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 2805396 1.87% 98.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 1723552 1.15% 99.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 514218 0.34% 99.91% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 137526 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 150113292 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 66740 0.75% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 6 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.75% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 8421993 94.18% 94.93% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 453824 5.07% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 58064867 47.22% 47.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 93414 0.08% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.32% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 52433900 42.64% 89.97% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 12332230 10.03% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 122955094 # Type of FU issued
system.cpu.iq.rate 0.258180 # Inst issue rate
system.cpu.iq.fu_busy_cnt 8942563 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.072730 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 405214220 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 117427083 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 85619955 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 23208 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 12528 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10296 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 131856805 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 652625 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 4242114 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 5511 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 31676 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 1637740 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 33981236 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 675243 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 3134378 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 11621778 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1344860 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 98019144 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 177250 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 19896895 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 13369840 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1412264 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 282212 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 925122 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 31676 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 351157 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 270951 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 622108 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 120868290 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 51786364 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2086804 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 226309 # number of nop insts executed
system.cpu.iew.exec_refs 64008543 # number of memory reference insts executed
system.cpu.iew.exec_branches 11843747 # Number of branches executed
system.cpu.iew.exec_stores 12222179 # Number of stores executed
system.cpu.iew.exec_rate 0.253798 # Inst execution rate
system.cpu.iew.wb_sent 119919333 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 85630251 # cumulative count of insts written-back
system.cpu.iew.wb_producers 47892202 # num instructions producing a value
system.cpu.iew.wb_consumers 88557277 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.179805 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.540805 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 19373634 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1482327 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 535963 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 146978914 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.528998 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.513466 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 118714103 80.77% 80.77% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 14514329 9.88% 90.64% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 3718532 2.53% 93.17% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 2215097 1.51% 94.68% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 1629859 1.11% 95.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 1057435 0.72% 96.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 1495738 1.02% 97.53% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 696782 0.47% 98.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 2937039 2.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 146978914 # Number of insts commited each cycle
system.cpu.commit.committedInsts 60459894 # Number of instructions committed
system.cpu.commit.committedOps 77751509 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27386881 # Number of memory references committed
system.cpu.commit.loads 15654781 # Number of loads committed
system.cpu.commit.membars 403574 # Number of memory barriers committed
system.cpu.commit.branches 10306383 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
system.cpu.commit.int_insts 69191543 # Number of committed integer instructions.
system.cpu.commit.function_calls 991261 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu 50274580 64.66% 64.66% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead 15654781 20.13% 84.91% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite 11732100 15.09% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 77751509 # Class of committed instruction
system.cpu.commit.bw_lim_events 2937039 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 239318561 # The number of ROB reads
system.cpu.rob.rob_writes 197472000 # The number of ROB writes
system.cpu.timesIdled 1764819 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 326125217 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 4575456172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 60309513 # Number of Instructions Simulated
system.cpu.committedOps 77601128 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 7.896574 # CPI: Cycles Per Instruction
system.cpu.cpi_total 7.896574 # CPI: Total CPI of All Threads
system.cpu.ipc 0.126637 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.126637 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 548833946 # number of integer regfile reads
system.cpu.int_regfile_writes 87707846 # number of integer regfile writes
system.cpu.fp_regfile_reads 8328 # number of floating regfile reads
system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
system.cpu.misc_regfile_reads 264312368 # number of misc regfile reads
system.cpu.misc_regfile_writes 1173237 # number of misc regfile writes
system.cpu.toL2Bus.throughput 58892733 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2658790 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2658789 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 607940 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2977 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961974 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5797376 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30926 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128827 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 7919103 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62745984 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85556470 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 42736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 216536 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 148561726 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 148561726 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 194772 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3129487727 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1474700416 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2550487184 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 20248986 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 74797546 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu.icache.tags.replacements 980898 # number of replacements
system.cpu.icache.tags.tagsinuse 511.584882 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 10510158 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 981410 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 10.709243 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 6868426250 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.584882 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999189 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999189 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 12553342 # Number of tag accesses
system.cpu.icache.tags.data_accesses 12553342 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 10510158 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 10510158 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 10510158 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 10510158 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 10510158 # number of overall hits
system.cpu.icache.overall_hits::total 10510158 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1061739 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1061739 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1061739 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1061739 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1061739 # number of overall misses
system.cpu.icache.overall_misses::total 1061739 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 14266290615 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 14266290615 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 14266290615 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 14266290615 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14266290615 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14266290615 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 11571897 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 11571897 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 11571897 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 11571897 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 11571897 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 11571897 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091752 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.091752 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.091752 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.091752 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.091752 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.091752 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13436.720903 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13436.720903 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13436.720903 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13436.720903 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13436.720903 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7331 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 116 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 335 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 21.883582 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 116 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80293 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 80293 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 80293 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 80293 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 80293 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 80293 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981446 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 981446 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 981446 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 981446 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 981446 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 981446 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11573178578 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 11573178578 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11573178578 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 11573178578 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11573178578 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 11573178578 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8964000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8964000 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8964000 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 8964000 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084813 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.084813 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084813 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.084813 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11791.966729 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11791.966729 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11791.966729 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11791.966729 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 64369 # number of replacements
system.cpu.l2cache.tags.tagsinuse 51363.817213 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1888922 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 129761 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 14.556932 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 2490733870000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 36937.336839 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 33.862464 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000252 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 8170.435646 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 6222.182012 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.563619 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000517 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124671 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.094943 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.783750 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65369 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3050 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54961 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997452 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 18802940 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 18802940 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 54086 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10683 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 967938 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 387449 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1420156 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 607940 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 607940 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 43 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 43 # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 8 # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 112904 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 112904 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 54086 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 10683 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 967938 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 500353 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1533060 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 54086 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 10683 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 967938 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 500353 # number of overall hits
system.cpu.l2cache.overall_hits::total 1533060 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 48 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 10729 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 23125 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133201 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133201 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 48 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143930 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 156326 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 48 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 12347 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143930 # number of overall misses
system.cpu.l2cache.overall_misses::total 156326 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3943500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 83000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 890764250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 800380499 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1695171249 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 583475 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 583475 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9778985980 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 9778985980 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3943500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 83000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 890764250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 10579366479 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 11474157229 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3943500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 83000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 890764250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 10579366479 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 11474157229 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 54134 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10684 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 980285 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 398178 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1443281 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 607940 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 607940 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2966 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 11 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 246105 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 246105 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 54134 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 10684 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 980285 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 644283 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1689386 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 54134 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 10684 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 980285 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 644283 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1689386 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000887 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000094 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012595 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026945 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016023 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.985502 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.985502 # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.272727 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.272727 # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541236 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541236 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000887 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000094 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012595 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.223396 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.092534 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000887 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000094 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012595 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.223396 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.092534 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82156.250000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 83000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72144.184822 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74599.729611 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73304.702659 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 199.615121 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 199.615121 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73415.259495 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73415.259495 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 73398.905038 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82156.250000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 83000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72144.184822 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73503.553665 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 73398.905038 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 59141 # number of writebacks
system.cpu.l2cache.writebacks::total 59141 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 66 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 66 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 48 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12336 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10663 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133201 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133201 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 48 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12336 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143864 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 156249 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 48 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12336 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143864 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 156249 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3351000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 71000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 734971750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 663368999 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1401762749 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29236922 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29236922 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8137112520 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8137112520 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3351000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 71000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 734971750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8800481519 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 9538875269 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3351000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 71000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 734971750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8800481519 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 9538875269 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 6435500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166942048250 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166948483750 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17498078150 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17498078150 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 6435500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184440126400 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184446561900 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026779 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015969 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985502 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985502 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.272727 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.272727 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541236 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541236 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.092489 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000887 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000094 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012584 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223293 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.092489 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 71000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59579.422017 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62212.229110 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60819.279287 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.368115 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.368115 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61088.974707 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61088.974707 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69812.500000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 71000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59579.422017 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.228765 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61049.192436 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 643771 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.993313 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 21491250 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 644283 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 33.356848 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 42393250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.993313 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 101573451 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 101573451 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 13743815 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13743815 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 7253892 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 7253892 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 242816 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 242816 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 20997707 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20997707 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 20997707 # number of overall hits
system.cpu.dcache.overall_hits::total 20997707 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 762201 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 762201 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 2968429 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 2968429 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 13530 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 13530 # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data 11 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data 3730630 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 3730630 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 3730630 # number of overall misses
system.cpu.dcache.overall_misses::total 3730630 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10170757825 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10170757825 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 136412874713 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 136412874713 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 184826749 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 184826749 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 180503 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 180503 # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 146583632538 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 146583632538 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 146583632538 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 146583632538 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 14506016 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 14506016 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10222321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10222321 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256346 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 256346 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247609 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247609 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 24728337 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 24728337 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 24728337 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 24728337 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052544 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.052544 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290387 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.290387 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052780 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052780 # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000044 # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total 0.000044 # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.150865 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.150865 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.150865 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.150865 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13343.931358 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 13343.931358 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45954.568802 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 45954.568802 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13660.513599 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13660.513599 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16409.363636 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16409.363636 # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 39291.924564 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 39291.924564 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 39291.924564 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 33676 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 25542 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2667 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 316 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.626922 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 80.829114 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 607940 # number of writebacks
system.cpu.dcache.writebacks::total 607940 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 376141 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 376141 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2719425 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2719425 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 3095566 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 3095566 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 3095566 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 3095566 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386060 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 386060 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249004 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 249004 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 11 # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 635064 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 635064 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 635064 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 635064 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4968476363 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4968476363 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11232028289 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 11232028289 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145250501 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145250501 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 158497 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 158497 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16200504652 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 16200504652 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16200504652 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 16200504652 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335641750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335641750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26891357119 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26891357119 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209226998869 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 209226998869 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047533 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047533 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12869.699951 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12869.699951 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45107.822722 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45107.822722 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11920.435043 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11920.435043 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14408.818182 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14408.818182 # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25510.034661 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 25510.034661 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1711484214589 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1711484214589 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1711484214589 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83038 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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