0ed3c84c7b
Usage: m5 writefile <filename> File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders.
149 lines
5.8 KiB
ArmAsm
149 lines
5.8 KiB
ArmAsm
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2003-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Nathan Binkert
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* Ali Saidi
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* Chander Sudanthi
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*/
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#define m5_op 0xEE
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#include "m5ops.h"
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#define INST(op, ra, rb, func) \
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.long (((op) << 24) | ((func) << 16) | ((ra) << 12) | (0x1 << 8) | (0x1 << 4) | (rb))
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/* m5ops m5func ra coproc 1 op=1 rb */
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#define LEAF(func) \
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.globl func; \
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func:
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#define RET \
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mov pc,lr
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#define END(func) \
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#define SIMPLE_OP(_f, _o) \
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LEAF(_f) \
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_o; \
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RET; \
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END(_f)
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#define ARM INST(m5_op, 0, 0, arm_func)
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#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
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#define QUIESCENS INST(m5_op, 0, 0, quiescens_func)
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#define QUIESCECYC INST(m5_op, 0, 0, quiescecycle_func)
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#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
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#define RPNS INST(m5_op, 0, 0, rpns_func)
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#define WAKE_CPU INST(m5_op, 0, 0, wakecpu_func)
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#define M5EXIT INST(m5_op, 0, 0, exit_func)
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#define INITPARAM INST(m5_op, 0, 0, initparam_func)
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#define LOADSYMBOL INST(m5_op, 0, 0, loadsymbol_func)
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#define RESET_STATS INST(m5_op, 0, 0, resetstats_func)
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#define DUMP_STATS INST(m5_op, 0, 0, dumpstats_func)
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#define DUMPRST_STATS INST(m5_op, 0, 0, dumprststats_func)
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#define CHECKPOINT INST(m5_op, 0, 0, ckpt_func)
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#define READFILE INST(m5_op, 0, 0, readfile_func)
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#define WRITEFILE INST(m5_op, 0, 0, writefile_func)
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#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
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#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
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#define ADDSYMBOL INST(m5_op, 0, 0, addsymbol_func)
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#define PANIC INST(m5_op, 0, 0, panic_func)
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#define WORK_BEGIN INST(m5_op, 0, 0, work_begin_func)
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#define WORK_END INST(m5_op, 0, 0, work_end_func)
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#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
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#define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
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#define AN_BEGIN INST(m5_op, an_begin, 0, annotate_func)
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#define AN_END INST(m5_op, an_end, 0, annotate_func)
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#define AN_Q INST(m5_op, an_q, 0, annotate_func)
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#define AN_RQ INST(m5_op, an_rq, 0, annotate_func)
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#define AN_DQ INST(m5_op, an_dq, 0, annotate_func)
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#define AN_WF INST(m5_op, an_wf, 0, annotate_func)
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#define AN_WE INST(m5_op, an_we, 0, annotate_func)
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#define AN_WS INST(m5_op, an_ws, 0, annotate_func)
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#define AN_SQ INST(m5_op, an_sq, 0, annotate_func)
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#define AN_AQ INST(m5_op, an_aq, 0, annotate_func)
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#define AN_PQ INST(m5_op, an_pq, 0, annotate_func)
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#define AN_L INST(m5_op, an_l, 0, annotate_func)
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#define AN_IDENTIFY INST(m5_op, an_identify, 0, annotate_func)
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#define AN_GETID INST(m5_op, an_getid, 0, annotate_func)
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.text
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SIMPLE_OP(arm, ARM)
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SIMPLE_OP(quiesce, QUIESCE)
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SIMPLE_OP(quiesceNs, QUIESCENS)
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SIMPLE_OP(quiesceCycle, QUIESCECYC)
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SIMPLE_OP(quiesceTime, QUIESCETIME)
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SIMPLE_OP(rpns, RPNS)
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SIMPLE_OP(wakeCPU, WAKE_CPU)
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SIMPLE_OP(m5_exit, M5EXIT)
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SIMPLE_OP(m5_initparam, INITPARAM)
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SIMPLE_OP(m5_loadsymbol, LOADSYMBOL)
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SIMPLE_OP(m5_reset_stats, RESET_STATS)
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SIMPLE_OP(m5_dump_stats, DUMP_STATS)
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SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS)
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SIMPLE_OP(m5_checkpoint, CHECKPOINT)
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SIMPLE_OP(m5_readfile, READFILE)
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SIMPLE_OP(m5_writefile, WRITEFILE)
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SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
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SIMPLE_OP(m5_switchcpu, SWITCHCPU)
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SIMPLE_OP(m5_addsymbol, ADDSYMBOL)
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SIMPLE_OP(m5_panic, PANIC)
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SIMPLE_OP(m5_work_begin, WORK_BEGIN)
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SIMPLE_OP(m5_work_end, WORK_END)
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SIMPLE_OP(m5a_bsm, AN_BSM)
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SIMPLE_OP(m5a_esm, AN_ESM)
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SIMPLE_OP(m5a_begin, AN_BEGIN)
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SIMPLE_OP(m5a_end, AN_END)
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SIMPLE_OP(m5a_q, AN_Q)
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SIMPLE_OP(m5a_rq, AN_RQ)
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SIMPLE_OP(m5a_dq, AN_DQ)
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SIMPLE_OP(m5a_wf, AN_WF)
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SIMPLE_OP(m5a_we, AN_WE)
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SIMPLE_OP(m5a_ws, AN_WS)
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SIMPLE_OP(m5a_sq, AN_SQ)
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SIMPLE_OP(m5a_aq, AN_AQ)
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SIMPLE_OP(m5a_pq, AN_PQ)
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SIMPLE_OP(m5a_l, AN_L)
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SIMPLE_OP(m5a_identify, AN_IDENTIFY)
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SIMPLE_OP(m5a_getid, AN_GETID)
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