gem5/src/mem
William Wang f9d403a7b9 MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
2012-03-30 09:40:11 -04:00
..
cache MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
config Fixes to get prefetching working again. 2009-02-16 08:56:40 -08:00
protocol build scripts: Made minor modifications to reduce build overhead time. 2012-03-06 19:07:41 -08:00
ruby MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
slicc Ruby: Add infrastructure for recording cache contents 2012-01-11 13:29:15 -06:00
bridge.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
bridge.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
Bridge.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
bus.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
bus.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
Bus.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
dram.cc Replace curTick global variable with accessor functions. 2011-01-07 21:50:29 -08:00
dram.hh stats: Fix all stats usages to deal with template fixes 2009-03-05 19:09:53 -08:00
fs_translating_port_proxy.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
fs_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
MemObject.py Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mport.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mport.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
packet.cc MemCmd: Add a command for invalidation requests to LSQ 2012-01-23 11:07:11 -06:00
packet.hh clang: Enable compiling gem5 using clang 2.9 and 3.0 2012-01-31 12:05:52 -05:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
packet_queue.cc MEM: Split SimpleTimingPort into PacketQueue and ports 2012-03-22 06:36:27 -04:00
packet_queue.hh MEM: Split SimpleTimingPort into PacketQueue and ports 2012-03-22 06:36:27 -04:00
page_table.cc Another merge with the main repository. 2012-01-07 02:16:37 -08:00
page_table.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
physical.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
physical.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
PhysicalMemory.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
port.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
port.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
port_proxy.cc MEM: Make all the port proxy members const 2012-02-29 04:47:51 -05:00
port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
qport.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
request.hh mem: fix cache stats to use request ids correctly 2012-02-12 16:07:39 -06:00
SConscript MEM: Split SimpleTimingPort into PacketQueue and ports 2012-03-22 06:36:27 -04:00
se_translating_port_proxy.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
se_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
tport.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
tport.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00