df973abef3
This patch takes a step towards an ISA-agnostic memory system by enabling the components to establish the page size after instantiation. The swap operation in the memory is now also allowing any granularity to avoid depending on the IntReg of the ISA.
51 lines
2.4 KiB
Python
51 lines
2.4 KiB
Python
# Copyright (c) 2012 Mark D. Hill and David A. Wood
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nilay Vaish
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from m5.SimObject import SimObject
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from System import System
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from m5.params import *
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from m5.proxy import *
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class Prefetcher(SimObject):
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type = 'Prefetcher'
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cxx_class = 'Prefetcher'
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cxx_header = "mem/ruby/structures/Prefetcher.hh"
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num_streams = Param.UInt32(4,
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"Number of prefetch streams to be allocated")
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pf_per_stream = Param.UInt32(1, "Number of prefetches per stream")
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unit_filter = Param.UInt32(8,
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"Number of entries in the unit filter array")
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nonunit_filter = Param.UInt32(8,
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"Number of entries in the non-unit filter array")
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train_misses = Param.UInt32(4, "")
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num_startup_pfs = Param.UInt32(1, "")
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cross_page = Param.Bool(False, """True if prefetched address can be on a
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page different from the observed address""")
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sys = Param.System(Parent.any, "System this prefetcher belongs to")
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