Andreas Hansson f85286b3de MEM: Add port proxies instead of non-structural ports ... Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh		2012-01-17 12:55:08 -06:00
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Benchmarks.py	ARM: Update config files for Android/BBench images available on website.	2011-12-15 00:43:35 -05:00
CacheConfig.py	configs: cache: add cache line size option	2011-02-23 14:26:55 -05:00
Caches.py	O3: Remove hardcoded tgts_per_mshr in O3CPU.py.	2011-12-01 00:15:22 -08:00
cpu2000.py	cpu2000: Add missing art benchmark to all	2012-01-09 18:08:20 -06:00
FSConfig.py	MEM: Add port proxies instead of non-structural ports	2012-01-17 12:55:08 -06:00
Options.py	Config: Add support for restoring using a timing CPU	2012-01-11 13:50:18 -06:00
Simulation.py	Config: Add support for restoring using a timing CPU	2012-01-11 13:50:18 -06:00
SysPaths.py	make rcS files read from the m5 source directory, not /dist.	2006-11-08 14:10:25 -05:00