238 lines
8 KiB
C++
238 lines
8 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include <vector>
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#include <list>
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#include "arch/isa_traits.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resources/inst_buffer.hh"
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#include "cpu/inorder/cpu.hh"
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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InstBuffer::InstBuffer(string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu,
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ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu)
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{ }
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void
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InstBuffer::regStats()
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{
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instsBypassed
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.name(name() + ".instsBypassed")
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.desc("Number of Instructions Bypassed.")
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.prereq(instsBypassed);
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Resource::regStats();
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}
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void
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InstBuffer::execute(int slot_idx)
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{
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ResReqPtr ib_req = reqMap[slot_idx];
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DynInstPtr inst = ib_req->inst;
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ThreadID tid = inst->readTid();
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int stage_num = ib_req->getStageNum();
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ib_req->fault = NoFault;
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switch (ib_req->cmd)
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{
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case ScheduleOrBypass:
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{
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int next_stage = stage_num + 1;
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int bypass_stage = stage_num + 2;
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bool do_bypass = true;
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if (!instList.empty()) {
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DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
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"because buffer isn't empty.\n",
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inst->seqNum, next_stage);
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do_bypass = false;
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} else if(cpu->pipelineStage[bypass_stage]->isBlocked(tid)) {
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DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
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"because stage %i is blocking.\n",
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inst->seqNum, next_stage);
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do_bypass = false;
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} else if(cpu->pipelineStage[bypass_stage]->
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stageBufferAvail() <= 0) {
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DPRINTF(InOrderInstBuffer, "[sn:%i] cannot bypass stage %i "
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"because there is no room in stage %i incoming stage "
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"buffer.\n", inst->seqNum, next_stage);
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do_bypass = false;
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}
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if (!do_bypass) { // SCHEDULE USAGE OF BUFFER
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DPRINTF(InOrderInstBuffer, "Scheduling [sn:%i] for buffer "
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"insertion in stage %i\n",
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inst->seqNum, next_stage);
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// Add to schedule: Insert into buffer in next stage
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int stage_pri = ThePipeline::getNextPriority(inst,
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next_stage);
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inst->resSched.push(new ScheduleEntry(next_stage,
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stage_pri,
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id,
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InstBuffer::InsertInst));
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// Add to schedule: Remove from buffer in next next (bypass)
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// stage
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stage_pri = ThePipeline::getNextPriority(inst, bypass_stage);
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inst->resSched.push(new ScheduleEntry(bypass_stage,
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stage_pri,
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id,
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InstBuffer::RemoveInst));
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} else { // BYPASS BUFFER & NEXT STAGE
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DPRINTF(InOrderInstBuffer, "Setting [sn:%i] to bypass stage "
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"%i and enter stage %i.\n", inst->seqNum, next_stage,
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bypass_stage);
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inst->setNextStage(bypass_stage);
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instsBypassed++;
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}
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ib_req->done();
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}
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break;
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case InsertInst:
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{
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bool inserted = false;
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if (instList.size() < width) {
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DPRINTF(InOrderInstBuffer, "[tid:%i]: Inserting [sn:%i] into "
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"buffer.\n", tid, inst->seqNum);
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insert(inst);
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inserted = true;
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} else {
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DPRINTF(InOrderInstBuffer, "[tid:%i]: Denying [sn:%i] request "
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"because buffer is full.\n", tid, inst->seqNum);
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std::list<DynInstPtr>::iterator list_it = instList.begin();
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std::list<DynInstPtr>::iterator list_end = instList.end();
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while (list_it != list_end) {
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DPRINTF(Resource,"Serving [tid:%i] [sn:%i].\n",
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(*list_it)->readTid(), (*list_it)->seqNum);
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list_it++;
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}
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}
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ib_req->done(inserted);
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}
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break;
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case RemoveInst:
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{
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DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing [sn:%i] from "
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"buffer.\n", tid, inst->seqNum);
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remove(inst);
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ib_req->done();
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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DPRINTF(InOrderInstBuffer, "Buffer now contains %i insts.\n",
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instList.size());
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}
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void
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InstBuffer::insert(DynInstPtr inst)
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{
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instList.push_back(inst);
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}
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void
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InstBuffer::remove(DynInstPtr inst)
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{
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std::list<DynInstPtr>::iterator list_it = instList.begin();
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std::list<DynInstPtr>::iterator list_end = instList.end();
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while (list_it != list_end) {
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if((*list_it) == inst) {
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instList.erase(list_it);
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break;
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}
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list_it++;
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}
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}
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void
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InstBuffer::pop(ThreadID tid)
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{
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instList.pop_front();
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}
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ThePipeline::DynInstPtr
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InstBuffer::top(ThreadID tid)
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{
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return instList.front();
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}
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void
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InstBuffer::squash(DynInstPtr inst, int stage_num,
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InstSeqNum squash_seq_num, ThreadID tid)
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{
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queue<list<DynInstPtr>::iterator> remove_list;
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list<DynInstPtr>::iterator list_it = instList.begin();
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list<DynInstPtr>::iterator list_end = instList.end();
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// Collect All Instructions to be Removed in Remove List
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while (list_it != list_end) {
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if((*list_it)->readTid() == tid &&
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(*list_it)->seqNum > squash_seq_num) {
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(*list_it)->setSquashed();
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remove_list.push(list_it);
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}
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list_it++;
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}
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// Removed Instructions from InstList & Clear Remove List
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while (!remove_list.empty()) {
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DPRINTF(InOrderInstBuffer, "[tid:%i]: Removing squashed [sn:%i] from "
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"buffer.\n", tid, (*remove_list.front())->seqNum);
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instList.erase(remove_list.front());
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remove_list.pop();
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}
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Resource::squash(inst, stage_num, squash_seq_num, tid);
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}
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