8949d813ff
configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
Add in default FUPool.
src/python/m5/objects/O3CPU.py:
Use defaults better. Also set checker parameters, and fix up a config bug.
--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b
41 lines
1.1 KiB
Python
41 lines
1.1 KiB
Python
from m5.SimObject import SimObject
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from m5.params import *
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from FuncUnit import *
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class IntALU(FUDesc):
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opList = [ OpDesc(opClass='IntAlu') ]
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count = 6
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class IntMultDiv(FUDesc):
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opList = [ OpDesc(opClass='IntMult', opLat=3),
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OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
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count=2
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class FP_ALU(FUDesc):
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opList = [ OpDesc(opClass='FloatAdd', opLat=2),
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OpDesc(opClass='FloatCmp', opLat=2),
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OpDesc(opClass='FloatCvt', opLat=2) ]
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count = 4
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class FP_MultDiv(FUDesc):
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opList = [ OpDesc(opClass='FloatMult', opLat=4),
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OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
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OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
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count = 2
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class ReadPort(FUDesc):
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opList = [ OpDesc(opClass='MemRead') ]
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count = 0
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class WritePort(FUDesc):
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opList = [ OpDesc(opClass='MemWrite') ]
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count = 0
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class RdWrPort(FUDesc):
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opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
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count = 4
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class IprPort(FUDesc):
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opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
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count = 1
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