4d77ea7a57
Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes. |
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| .. | ||
| alpha | ||
| arm | ||
| mips | ||
| power | ||
| sparc | ||
| x86 | ||
| isa_parser.py | ||
| micro_asm.py | ||
| micro_asm_test.py | ||
| SConscript | ||